1,720,963 research outputs found
Modeling, Design and Characterization of a new low Jitter Analog Dual Tuning LC-VCO PLL Architecture
No full textThis paper describes the modeling, design, and characterization of a low-jitter 2.4-GHz LC-VCO PLL architecture realized in a standard 0.12-mu m CMOS technology. It features an analog dual control loop for fine and coarse VCO tuning that allows very low VCO gain (60 MHz/V) for noise rejection while maintaining a wide tuning range. The coarse input of the VCO is driven by an analog circuit that adjusts the VCO gain in a continuous manner. Measurements demonstrate an integrated jitter of 0.74 ps that is 43% lower compared to results from a standard PLL topology (STD PLL) with a single control loop. The PLLs have the same bandwidth and output frequency range and were built on the same wafer for comparison. The circuit area of the proposed LC-VCO PLL is 0.7 mm(2) and the power consumption is 32 mW. The area and power consumption of the proposed LC-VCO PLL are less than 1% larger compared to the STD PLL
Dynamics of the modulational instability in semiconductor doped glasses
No full textWe study the dynamics of the induced modulational instability in waveguides with saturable, third order, nonlinearity. The theoretical and numerical analysis reveal interesting features which could be exploited for all optical switching and processing
An Integrated Divide-by-Two Direct Injection-Locking Frequency Divider for Bands S Through Ku
No full textIn this work, direct injection locking is applied to
a ring oscillator topology to design a wideband divide-by-two
frequency divider circuit with a locking range covering bands S
through Ku, namely input frequencies from 2 to 16 GHz. A thorough
analysis is carried out: a behavioral model is developed that
allows us to capture the operation of the two-stage differential ring
oscillator. The mixing operation inherent in the direct injection
scheme is deeply investigated and compared with tail injection
locking. The design guidelines leading to a wide locking range are
derived and exploited. Prototypes implemented in a digital 65-nm
CMOS technology draw 1.6 mA from a 1.2-V supply. Since the
design is inductorless, the divider area is as low as 130 um^2. The
output phase noise tracks the reference’s one with the expected
6-dB difference over the entire range of operation frequencies
A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS
No full textA GSM-compliant local oscillator consuming a tiny die area of only 0.059 mm2 and drawing 9 mA from a 1.2 V supply has been designed in a 65-nm CMOS process using thin-oxide devices only. The system is made of a 13 to 15 GHz LC VCO followed by a divide-by-four injection-locked frequency divider. The divider employs a ring oscillator-based topology leading to a two octave locking range with limited area and power consumption. The phase noise at the output of the system is less than -133 dBc/Hz at 3 MHz offset over the tuning range
A 0.06 mm^2 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS
No full textA GSM-compliant local oscillator consuming a tiny
die area of only 0.06 mm^2 and drawing 9 mA from a 1.2 V supply
has been designed in a 65 nm CMOS process using thin-oxide devices
only. The system is made of a 13 to 15 GHz LC VCO followed
by a divide-by-four injection-locked frequency divider. The
divider employs a ring oscillator-based topology leading to a two
octave locking range with limited area and power consumption.
The phase noise at the output of the divider is below -133 dBc/Hz
at 3 MHz offset over the tuning range
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