1,721,434 research outputs found
Infrastructures and Algorithms for Testable and Dependable Systems-on-a-Chip
Full text linkEvery new node of semiconductor technologies provides further miniaturization and higher performances, increasing the number of advanced functions that electronic products can offer. Silicon area is now so cheap that industries can integrate in a single chip usually referred to as System-on-Chip (SoC), all the components and functions that historically were placed on a hardware board. Although adding such advanced functionality can benefit users, the manufacturing process is becoming finer and denser, making chips more susceptible to defects. Today’s very deep-submicron semiconductor technologies (0.13 micron and below) have reached susceptibility levels that put conventional semiconductor manufacturing at an impasse. Being able to rapidly develop, manufacture, test, diagnose and verify such complex new chips and products is crucial for the continued success of our economy at-large. This trend is expected to continue at least for the next ten years making possible the design and production of 100 million transistor chips.
To speed up the research, the National Technology Roadmap for Semiconductors identified in 1997 a number of major hurdles to be overcome. Some of these hurdles are related to test and dependability.
Test is one of the most critical tasks in the semiconductor production process where Integrated Circuits (ICs) are tested several times starting from the wafer probing to the end of production test. Test is not only necessary to assure fault free devices but it also plays a key role in analyzing defects in the manufacturing process. This last point has high relevance since increasing time-to-market pressure on semiconductor fabrication often forces foundries to start volume production on a given semiconductor technology node before reaching the defect densities, and hence yield levels, traditionally obtained at that stage. The feedback derived from test is the only way to analyze and isolate many of the defects in today’s processes and to increase process’s yield.
With the increasing need of high quality electronic products, at each new physical assembly level, such as board and system assembly, test is used for debugging, diagnosing and repairing the sub-assemblies in their new environment. Similarly, the increasing reliability, availability and serviceability requirements, lead the users of high-end products performing periodic tests in the field throughout the full life cycle.
To allow advancements in each one of the above scaling trends, fundamental changes are expected to emerge in different Integrated Circuits (ICs) realization disciplines such as IC design, packaging and silicon process. These changes have a direct impact on test methods, tools and equipment. Conventional test equipment and methodologies will be inadequate to assure high quality levels. On chip specialized block dedicated to test, usually referred to as Infrastructure IP (Intellectual Property), need to be developed and included in the new complex designs to assure that new chips will be adequately tested, diagnosed, measured, debugged and even sometimes repaired.
In this thesis, some of the scaling trends in designing new complex SoCs will be analyzed one at a time, observing their implications on test and identifying the key hurdles/challenges to be addressed. The goal of the remaining of the thesis is the presentation of possible solutions. It is not sufficient to address just one of the challenges; all must be met at the same time to fulfill the market requirements
Combining cluster sampling and ACE analysis to improve fault-injection based reliability evaluation of GPU-based systems
Full text linkComputing capability demand has grown massively in recent years. Modern GPU chips are designed to deliver extreme performance for graphics and for data-parallel general purpose computing workloads (GPGPU computing) as well. Many GPGPU applications require high reliability, thus reliability evaluation has become a crucial step during their design. State-of-the-art techniques to assess the reliability of a system are fault injection and ACE analysis. The former can produce accurate results despite eternal time while the latter is very fast but it lacks accuracy of the results. In this paper we introduce a new sampling methodology based on cluster sampling that enables the exploitation of ACE analysis to accelerate the fault injection process. In our experiments we demonstrate that state-of-the-art fault injection techniques, generating random faults according to a uniform distribution, is outperformed by the proposed sampling technique, thus enabling several advantages in terms of accuracy and evaluation time. To quantify the introduced benefits we analyzed the micro-architecture reliability of an AMD Southern Islands GPU in presence of single bit upset affecting the vector register file for 6 benchmarks. One of the most important achievements is that considering all the benchmarks, on average, we are one order of magnitude faster/more accurate than uniform-sampling-based techniques in case of non exhaustive fault injection campaigns, while more than two orders of magnitude in case of exhaustive campaigns
Current highlights on solid pseudopapillary neoplasm of the pancreas
Full text linkSolid pseudopapillary neoplasm of the pancreas is a low-grade malignant tumor that predominantly affects young women in their third and fourth decade. Etiology and risk factors are unknown. Clinical symptoms are aspecific and most commonly due to mass effect. Diagnosis is made by computed tomography scan or magnetic resonance imaging and histological characterization is obtained by endoscopic ultrasound-guided fine needle biopsy. Microscopically, these lesions are composed by both solid and pseudopapillary structures with necrotic and hemorrhagic areas. Occasionally, the biological behavior is aggressive with tumor recurrence and distant metastasis. Usually, curative R0 surgical resection is the best option able to provide long term survival even in advanced disease. Unresectable disease is the main predictor of poor prognosis. Chemotherapy and radiotherapy regimens are not well standardized. However, they could be effective in reducing tumor size as neoadjuvant treatment or disease control in palliative setting. Although complete surgical resection provides a cure rate of > 95%, considering young age of the patients and morbidity associated to pancreatic surgery, further studies are needed to better investigate risk factors and responsiveness to hormones in order to allow early diagnosis and follow up strategies that could avoid unnecessary surgery in less aggressive disease
Effective length of the arterial circulation determined in the dog by aid of a model of the systemic input impedance
No full textProceedings of the 13th Annual Northeast Bioengineering Conference, Philadelphia, P
A Methodology for Co-simulation-Based Optimization of Biofabrication Protocols
Full text linkBiofabrication processes are complex and often unsatisfactory. Trial-and-error methods are costly and yield only incremental innovation, starting from sub-optimal and poorly represented existing processes. Although computational techniques might support efficient process design to find optimal process configurations, intelligent computational approaches must comprise biological complexity to provide meaningful insights. This paper proposes a novel co-simulation-based optimization methodology for the systematic design of protocols for cell culture and biofabrication. The proposed strategy integrates evolutionary computation and simulation for efficient design space exploration and assessment of candidate protocols. A generic library supports the modular and flexible composition of multiscale and multidomain co-simulation scenarios. The feasibility of the presented approach was demonstrated in the automatic generation of rotocols for the biofabrication of an epithelial cell monolayer. The results are twofold. First, the prototype co-simulation library helps build flexible, loosely coupled simulation scenarios. Second, the in-silico experimentation on the use case shows that the proposed approach is a viable first step towards standard and automated design in biofabrication
A low-cost approach for determining the impact of Functional Approximation
Full text linkApproximate Computing (AxC) trades off between the level of accuracy required by the user and the actual precision provided by the computing system to achieve several optimizations such as performance improvement, energy, and area reduction etc.. Several AxC techniques have been proposed so far in the literature. They work at different abstraction level and propose both hardware and software implementations. The common issue of all existing approaches is the lack of a methodology to estimate the impact of a given AxC technique on the application-level accuracy. In this paper, we propose a probabilistic approach to predict the relation between component-level functional approximation and application-level accuracy. Experimental results on a set of benchmark application show that the proposed approach is able to estimate the approximation error with good accuracy and very low computation time
Guest Editorial: Special section on emerging trends and computing paradigms for testing, reliability and security in future VLSI systems
Full text linkWith the rapid advancement of computing technologies in all domains (i.e., handheld devices, autonomous vehicles, medical devices, and massive supercomputers), testability, reliability and security of electronic systems are crucial issues to guarantee safeness of human life. Emerging technologies coupled with new computing paradigms (e.g., approximate computing, neuromorphic computing, in-memory computing) are together exacerbating these problems posing significant challenges to researchers and designers. To address this increased complexity in the hardware testing/reliability/security domain, it is imperative to employ design and analysis methods working at all levels of abstraction, starting from the system level down to the gate level.
In this context, the selected papers span from the important field of the yield analysis and modeling, which is becoming fundamental for the manufacturing of modern technologies to the error detection, correction and recovery when the new devices are operative on field. At the same time, papers do not forget that the fault tolerance can be achieved by a cross-layer approach to the dependability that includes the analysis of the effect of faults and the techniques and methodologies to deploy more resilient devices by means of hardening of the design. Eventually, the dependability of the systems is nowadays deeply linked with the security aspects, including the impact on the design trade-offs and the test and validation.
The IEEE VLSI Test Symposium (VTS) invited the highest-ranked papers to be included in this special issue of IEEE Transactions on Emerging Technologies in Computing (TETC) in 2020. All aspects of design, manufacturing, test, monitoring and securing of systems affected by defects and malicious attacks are covered by the accepted paper.
It is our great pleasure to publish this special issue containing 12 high-quality papers covering all aspects of the emerging trends on testing and reliability:
- FTxAC: Leveraging the Approximate Computing Paradigm in the Design of Fault-Tolerant Embedded Systems to Reduce Overheads by Aponte-Moreno, Alexander; Restrepo-Calle, Felipe; Pedraza, Cesar, the design of Fault-Tolerant systems is exploited by means of approximate computing techniques to reduce the implicit overhead of the common redundancy.
- A Statistical Gate Sizing Method for Timing Yield and Lifetime Reliability Optimization of Integrated Circuits by Ghavami, Behnam; Ibrahimi, Milad; Raji, Mohsen, the reliability of CMOS devices is improved tackling the joint effect of process variation and transistor aging.
- 3D Ring Oscillator based Test Structures to Detect a Trojan Die in a 3D Die Stack in the Presence of Process Variations by Alhelaly, Soha; Dworak, Jennifer; Nepal, Kundan; Manikas, Theodore; Gui, Ping; Crouch, Alfred, the issue of Trojan insertion into 3D integrated circuits has been explored from the use of in-stack circuitry and various testing procedures point of view, showing their detection capability.
- Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory by Liu, Peng; You, Zhiqiang; Wu, Jigang; Elimu, Michael; Wang, Weizheng; Cai, Shuo; Han, Yinhe, a new parallel March-like test is proposed to test CMOS Molecular architectures.
- Attacks toward Wireless Network-on-Chip and Countermeasures by Biswas, Arnab Kumar; Chatterjee, Navonil; Mondal, Hemanta; Gogniat, Guy; DIGUET, Jean-Philippe, Wireless Network-on-Chip security vulnerabilities are described and their countermeasures proposed.
- A Novel TDMA-Based Fault Tolerance Technique for the TSVs in 3D-ICs Using Honeycomb Topology (by Ni, Tianming; Yang, Zhao; Chang, Hao; Zhang, Xiaoqiang; Lu, Lin; Yan, Aibin; Huang, Zhengfeng; Wen, Xiaoqing) proposes a chain-type time division multiplexing access (TDMA)-based fault tolerance technique showing huge area overheads reduction.
- Design and analysis of secure emerging crypto-hardware using HyperFET devices by Delgado-Lozano, Ignacio María; Tena-Sánchez, Erica; Núñez, Juan; Acosta, Antonio J., Power Analysis attacks against FinFET device have been tackled by incorporating HyperFET devices to deliver an x25 factor security level improvement.
- Detection, Location, and Concealment of Defective Pixels in Image Sensors by TAKAM TCHENDJOU, Ghislain; SIMEU, Emmanuel, image sensors are empowered with online diagnosis and self-healing methods to improve their dependability.
- Defect and Fault Modeling Framework for STT-MRAM Testing by Wu, Lizhou; Rao, Siddharth; Taouil, Mottaqiallah; Cardoso Medeiros, Guilherme; Fieback, Moritz; Marinissen, Erik Jan; Kar, Gouri Sankar; Hamdioui, Said, a framework to derive accurate STT-MRAM fault models is described, together with its employment to model resistive defects in interconnect and pinhole defects in MTJ devices, allowing test solutions for detecting those defects.
- Online Safety Checking for Delay Locked Loops via Embedded Phase Error Monitor by Huang, Shi-Yu; Chu, Wei, the Automotive Safety Integrity Level (ASIL) is targeted by proposing a phase error monitoring scheme for Delay-Locked Loops (DLLs).
- Protecting Memories against Soft Errors: The Case for Customizable Error Correction Codes by Li, Jiaqiang; Reviriego, Pedro; Xiao, Li; Wu, Haotian, the memory protection is supported by a tool able to automate the error correction code design.
- Autonomous Scan Patterns for Laser Voltage Imaging by Tyszer, Jerzy; Cheng, Wu-Tung; Milewski, Sylwester; Mrugalski, Grzegorz; Rajski, Janusz; Trawka, Maciej, authors demonstrate how to reuse on-chip EDT compression environment to generate and apply Laser Voltage Imaging-aware scan patterns for advanced contactless test procedures.
We sincerely hope that you enjoy reading this special issue, and would like to thank all authors and reviewers for their tremendous efforts and contributions in producing these high-quality articles. We also take this opportunity to thank the IEEE Transactions on Emerging Topics in Computing (TETC) Editor-in-Chief (EIC) Prof. Cecilia Metra, past Associate Editor Ramesh Karri, the editorial board, and the entire editorial staff for their guidance, encouragement, and assistance in delivering this special issue
A collision timing monitor for SuperKEKB
No full textThe analysis of beamstrahlung radiation, emitted from a beam of charged particles due to the electromagnetic interaction with a second beam of charged particles, provides a diagnostic tool that can be used to monitor beam–beam collisions in a e+e− storage ring. In this paper we show that the beamstrahlung time profile is related to the timing of the collisions and the length of the beams, and how its measurement can be used to monitor and optimize collisions at the interaction point of the SuperKEKB collider. The method has a unique passive monitor capability, since it allows to monitor the timing of the collision without disturbing (scanning) the beam–beam timing, which needs to be measured to unprecedented accuracy at SuperKEKB. To measure the time dependence of beamstrahlung, we describe a method based on nonlinear frequency mixing in a nonlinear crystal of beamstrahlung radiation with photons from a pulsed laser. We demonstrate that the method allows to measure and optimize the relative timing and length of the colliding bunches with 3% accuracy
Customer satisfaction in a public service of work medicine for harassed workers
No full textDeep changes in labor market, re-engineering of organizations and the considerable growing of dysfunctional relations at work, have severe consequences in workers' health. Many public services of work medicine had recently born offering clinical assistance, evaluations, certifications and counseling. In order to adjust the quality and the efficiency of services for harassed workers, an exploratory research in customer satisfaction was run. 66 workers who had been helped by a public service of work medicine were interviewed filling up a questionnaire made of 14 items. Results had shown that there are many difficulties in access these services: workers are sent mostly by lawyers and others clinical specialist, when their job situation or their mental health are compromised. Workers access these services especially to obtain certifications that can be later utilized in law controversy or in illness evaluation. The most useful aspect for customers is the possibility to have assistance and councils deciding how to front the situation, while satisfaction is strictly linked to the ability of the service to answer to customers' need of sustain. Results underline that an improvement of efficacy would be reached with prolonged assistance and a local distribution on the territory
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