1,720,971 research outputs found
ARM-based embedded system for SpaceFibre Link Analyzer
No full textModern and forthcoming space missions are demanding multi-payload satellites working at very high speed. The current standardized technology, SpaceWire, is no more able to fulfil the requirement of such data-rates often beyond 1Gb/s. SpaceFibre is the upcoming standard supported by the European Space Agency (ESA) for on-board satellite high-speed communications, allowing for data rates one or two orders of magnitude higher than SpaceWire. SpaceFibre also supports integrated Quality of Service (QoS) and Fault Detection, Isolation and Recovery (FDIR) mechanisms, allowing for a highly reliable communication.
However, the abovementioned features make the development of new SpaceFibre-based devices undoubtedly complex and the there is a strong necessity for a test equipment to validate such devices. In this paper, an ARM-based SpaceFibre Link Analyzer is presented. It can be used to support the development of new SpaceFibre and SpaceWire related devices as well as to test complex network systems based on them
Independent implementation of a SpaceFibre CODEC compliant with the standard draft F3
No full textThe current SpaceFibre draft standard F3 is the result of many iterations, reviews and prototyping. Despite the different revisions, there are not many independent implementations to prove that the current standard version is correctly and easily implementable. In this activity, the SpaceFibre draft standard F3 has been taken as the only input for the implementation of a SpaceFibre CODEC. This allows providing genuine feedback on the current specification and to effectively prove its implementability. In this presentation, the current status of the SpaceFibre activity will be presented together with the main findings and feedback on the current SpaceFibre draft standard F3. Implementation of a demonstrator using a Xilinx-based platform will be possibly shown
Verification environment for a SpaceFibre CODEC compliant with the standard draft F3
No full textThe University of Pisa has been collaborating with ESA for an independent development of a SpaceFibre CODEC IP, in order to review and consolidate the standard draft F3. A complete SpaceFibre CODEC IP was implemented, verified and its interoperability has been tested with a hardware demonstrator.
In this presentation, the current status of the SpaceFibre activity carried out by the University of Pisa will be reported, with a particular focus on the verification approach adopted and the main results on this topic
A Novel Parallel 8B/10B Encoder: Architecture and Comparison with Classical Solution
No full text8B/10B is an encoding technique largely used in different communication protocols, with several advantages such as zero DC bias. In the last years transmission rates have grown rapidly, thus the need of encoders with better performance in terms of throughput, area and power consumption raised rapidly. In this article we will present and discuss the architecture of two symbols parallel encoder, comparing it with a classical pipelined solution
A SpaceFibre multi lane codec System on a Chip: Enabling technology for low cost satellite EGSE
No full textIn the last few years, data rate requirement on on-board satellite communication systems significantly grown. The need of high speed networks led to the birth of the SpaceFibre protocol, which is able to run at several Gigabit per second and operates over both optical fibre and copper cables. A key feature of SpaceFibre is the possibility to have multi lane link, which increases the overall achievable data rate and link reliability. The growing complexity of satellite payload communication systems requires the definition an accurate monitoring and testing system. In this paper a multi lane SpaceFibre interface integrated in a System on a Chip is presented as enabling technology for an electrical ground segment equipment
Integration of Twin Models in UVM Verification IPs for Space Telecommunication Systems
No full textIn the dynamic fields of semiconductor design and digital system development, effective verification procedures are in high demand. In particular, functional verification is essential for space systems to guarantee mission success, prevent errors in intricate environments, and uphold the reliability vital for effective space exploration. Testing phase results extremely challenging because of the high complexity of systems, often due to the intricate interplay of hardware, software, and environmental factors, impeding comprehensive validation. This paper presents an innovative methodology for the functional verification of systems involved in space telecommunications: this is based on the development and integration of software Twin Models within advanced and automated verification environments, with the dual purpose of simplifying the stimulation of the Design Under Test (DUT) and producing instant-by-instant expected behavior. The proposed solutions are developed in SystemVerilog Hardware Verification Language (HVL) and are fully compliant with Universal Verification Methodology (UVM) standard. As proof of the effectiveness and applicability of this approach, examples of verification environments for different systems are given, including high-speed interfaces, such as SpaceWire (SpW) CODECs, and high-speed encoders and modulators for both Direct-to-Earth and inter-satellite communications applications. A test campaign was conducted for all these systems, and using the Twin Models made it possible to achieve 100% of both functional and code coverage. The final result is a significant simplification in the creation of tests and DUT debugging and a very highly flexible, self-checking, and automated verification environment able to test any possible DUT configuration efficiently
A Software Defined Radio Transponder for Low-Orbit Satellite Communications
No full textThe paper presents a Software-Defined Radio (SDR) Telemetry, Tracking & Command (TT&C) transponder for Low Earth Orbit (LEO) satellites, named STAR. STAR implements A/D and D/A conversion at IF and baseband digital signal processing for telecommand reception and telemetry transmission, i.e., multi-standard
(de)modulation, channel (de)coding, and control. An S/X-band transceiver is connected to the IF ports of
STAR for RF frequency up/down conversion. Preliminary results for a proof-of-concept FPGA
implementation are presented
Design and implementation of test equipment for SpaceFibre links: SpaceFibre
No full textSpaceFibre is the upcoming European standard for on-board high-speed communications. The need for data-rate beyond 1 Gb/s is already present in space missions, and it is currently fulfilled by non-standard approaches based on Serialiser/Deserialiser components such as Texas Instruments TLK2711. The SpaceFibre standard also integrates Quality of Service and Fault Detection, Isolation and Recovery mechanisms, which allow a highly reliable communication, suitable for space systems. The abovementioned features make the SpaceFibre standard undoubtedly complex; therefore an adequate test equipment is necessary for the validation of systems based on this standard. In this paper, a test equipment for SpaceFibre links is presented. This is designed to support the development of new SpaceFibre devices, as well as complex systems based on SpaceFibre. A system demonstrator was implemented to validate the equipment features
A serial high-speed satellite communication CODEC: Design and implementation of a SpaceFibre interface
Full text linkIn the last few years, satellite on-board data handling bandwidth requirements grew significantly, as well as production volume of these systems. A series of different protocols currently try to answer this need. In particular, the European Space Agency developed an open protocol solution: SpaceFibre. The SpaceFibre protocol can sustain a line rate of 6.25 Gb/s per lane (up to 16 lanes). It offers advanced and flexible Quality-of-Service features, as well as Fault Detection Isolation and Recovery services. The protocol structure has been developed so that full hardware implementation of its core layers is straightforward, granting high performances at low price
in terms of complexity and power consumption, one of the most stringent requirements in space applications. In this paper, a FPGA implementation on both rad-hardened (RTAX2000, RTG4, Virtex-5) and commercial (ZYNQ 7000) devices of the SpaceFibre CODEC is presented together with its verification environment and a hardware validation set-up. Particular attention is given to the trade-off between resources utilisation, power consumption and CODEC configurations, in order to enable future system adopters to efficiently explore the design space
A real-time FPGA-based solution for binary image thinning
No full textThis paper presents an optimized FPGA implementation for real-time binary image thinning algorithm. The reference thinning technique is based on iterated comparisons with a set of eight 3×3 binary masks. In the proposed architecture, the processing logic and the internal memory are implemented in a way that themask matching on each 3×18 image segment can be done in parallel within a single clock cycle. This optimization entails a reduction of more than one order of magnitude in terms of execution cycles with respect to the original algorithm. The algorithm was implemented on an ALTERA Stratix II EP2S30 FPGA. The resource occupation of the thinning block and the dedicated memory controllers is 4% at 100MHz clock frequency. The proposed solution produces the output in 0.03 s on a standard PAL 720 × 576, allowing for further real-time processing
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