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Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits
This work extends to the switch level the verification
and testing techniques based upon boolean satisfiability
(SAT), so that SAT-based methodologies can be applied
to circuits that cannot be well described at the gate level.
The main achieved goal was to define a boolean model
describing switch-level circuit operations as a SAT problem
instance, to be applied to combinational equivalence checking
and bridging-fault test generation. Results are provided
for a set of combinational CMOS circuits, showing the feasibility
of SAT-based verification and testing of switch-level
circuits
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