1,720,974 research outputs found
A VLSI inner product macrocell
No full textMicrocontrollers for embedded computer applications require a library of dedicated macrocells for specific applications. Arithmetic and basic DSP computations may be too inefficient when computed by software on the core CPU of the microcontroller. The architecture of a VLSI macrocell, for the ST9 microcontroller (8 bit), dedicated to the computation of the inner (scalar) product of two vectors of integer numbers and based on the multiply and accumulate algorithm, is here defined and developed. The arithmetic core of the macrocell is an integer pipeline. This macrocell fully interfaces to the ST9 environment and is optimised so as to achieve the maximum performances compatible with the bandwidth of the bus of ST9 and the minimum consumption of silicon area. The macrocell is implemented in CMOSM5H technology (0.7 μ channel width) and its performances, measured in terms of silicon area and throughput, are evaluated
A serial-input serial-output bit-sliced convolver
No full textA novel convolver is presented in which both samples and results are in serial form, while coefficients are stored in internal registers. The convolver is composed of an array of multiplier-accumulator subunits which operate in a carry-save, serial/parallel mode. The sample bits are broadcast to all subunits, each one executing the multiplication with the stored coefficient and accumulating the product with the result received from the preceding unit. The structure can be shown to be decomposable in bit-slices; a stack of slices can be programmed as a convolver for prescribed sample and coefficient bit-length under the control of a configuration register. Faulty slices can be neutralized by variables stored in a second register
A fast pipelined FFT unit
No full textThis paper is dedicated to the presentation of the architecture of a VLSI butterfly processing element, for computing FFT in serial arithmetic. This butterfly PE uses complex samples and weights, with real and imaginary parts represented separately in full fractional two's complement form. The PE is based on a compact serial/parallel to serial complex multiplier, which optimises complex multiplication by merging the generation and accumulation of partial products. The structure of the multiplier and the PE is presented; their performances are evaluated, including the possibility of reconfiguration, fault detection and fault tolerance
A VLSI inner product macrocell
No full textMicrocontrollers for embedded computer applications require a library of dedicated macrocells for specific applications. Arithmetic and basic digital signal processor (DSP) computations may be too inefficient when computed by software on the core central processing unit (CPU) of the microcontroller. Here the architecture of a VLSI macrocell is defined and developed for the ST9 microcontroller (8 bits), for the computation of the inner (scalar) product of two vectors of integer numbers based on the multiply/accumulate algorithm. The arithmetic core of the macrocell is an integer pipeline. This macrocell fully interfaces to the ST9 environment and is optimized so as to achieve the maximum performances compatible with the bandwidth of the bus of ST9 and the minimum consumption of silicon area. The macrocell Is implemented in CMOSM5H technology (0.7 /spl mu/ channel width) and its performances, measured in terms of silicon area and throughput, are evaluated
Fast arithmetic and fault tolerance in the FERMI system
No full textThe FERMI is a data acquisition system for calorimetry experiments in high energy physics at the LHC, CERN. The system contains a large number of acquisition channels, with a precision of 16 bits and a sampling rate of 40 MHz. A large part of the information driven by the channels is processed locally, to reduce the amount of data. This requires to cluster several channels by adding them. The paper presents the design of a fast, low cost adder chip, based on the implementation of column compression techniques for the computation of integer addition. Since the system is operating in a radiation-hard environment, fault tolerance (namely fault detection) is implemented by means of arithmetic codes
Testing of serial input convolvers
No full textTwo bit-serial convolver architectures computing serial discrete convolution are presented. Their testability characteristics are studied. A linear time complexity test procedure for both structures is developed. It is shown that functional reconfigurability of these architectures represents an advantage for testability. The test procedure is in fact based on partitioning the architectures into simpler structures and testing them separately
Column compression pipelined multipliers
No full textThe paper presents a study on the introduction of pipelining in parallel VLSI multipliers, built according to the column compression (CC) design techniques. A number of CC multiplier schemes have been proposed in the literature, aimed at reducing the number of stages of adders necessary to compute a multiplication. More recently CC multiplier schemes aimed at optimising the required silicon area, the regularity and the locality of the interconnections among the adders, have been proposed. The paper affords the introduction of pipelining in these last structures and compares the obtained results with existing structures, in terms of required number of components and operation frequenc
Bit-serial fault-tolerant architectures for convolution and polynomial evaluation
No full textThe authors present three distinct serial-input serial-output architectures: two for the computation of discrete convolution (bit-sliced and polyphase convolvers) and one for polynomial evaluation (polynomiers). These devices operate in serial fixed point natural arithmetic. All architectures are characterized by a bit-sliced structure that makes possible easy design and testing. The regular, uniform bit-slices also give the possibility of introducing functional reconfigurability and fault tolerance. For all these reasons, the proposed three architectures are good candidates for VLSI and WSI (wafer scale integration) implementation. Prototypal layouts, testing procedures, and statistical analysis have been developed for the evaluation of the architecture performances, the introduction of fault tolerance, and the study of the obtained fault coverage, reliability, and fabrication yield
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