1,721,240 research outputs found
Test Sequences Embedding with Cellular Automata
No full textTest Sequences Embedding with Cellular Automat
Test Generation for Stuck-at and Gate-Delay Faults in Sequential Circuits: a Mixed Functional/Structural Method
No full textmissin
Fault Detection in Sequential Circuits through Functional Testing
No full textThe authors present a new functional test pattern generation algorithm for sequential architectures based on their finite state machine specification. The algorithm is based on a functional fault model. Each transition of the finite state machine is analyzed and state distinguishing sequences are adopted to observe their final state. Overlapping of test sequences is performed in order to reduce test length. Experimental results have shown the effectiveness of the test algorithm both at the functional level and at the gate level. The relations between synthesis, fault coverage and testing will be also determined
Test Pattern Embedding in Sequential Circuits through Cellular Automata
No full textThe embedding of test patterns into a sequential circuit is the main topic of this paper. Deterministic test patterns for the sequential circuit under test are chosen to be embedded into hybrid cellular automata (CA). Test identification and CA synthesis are performed in parallel thus overcoming results achieved by embedding pre-computed vectors. The theory of sequential test generation under such a constraint is provided and the feasibility of the proposed testing methodology is shown on benchmarks
Behavioral Test Generation for Test Embedding
No full textBehavioral Test Generation for Test Embeddin
A Functional Approach to Delay Fault Test Generation for Sequential Circuits
No full textIn this paper we present an analysis of the coverage of delay faults in sequential circuits by a functional test pattern generator. Relationships are investigated between a functional fault model and delay faults, with correlations to the stuck-at fault coverage. Undetected faults are identified and an algorithm to improve the delay fault coverage is proposed. The final approach generates a functional test for sequential circuits with optimization and reaches complete coverage of detectable delay faults with short tests
A Complete Testing Strategy Based on Interacting and Hierarchical FSMs
No full textControl-dominated architectures are usually specify, in a hardware description language (HDL), by means of a composition of FSMs. This paper presents two FSMs based models which can be extracted from a Statechart or a HDL description. Such models are compared to the description of the device at the different abstraction levels of a standard synthesis pow. This comparison simplifies the testing problem producing a complete testing strategy that uses functional information to perform scan insertion, redundancies removal and test pattern generation even for such devices which cannot be satisfactorily analyzed at the gate level
Implicit Testability Techniques for VHDL Based ASIC Design
No full textImplicit Testability Techniques for VHDL Based ASIC Desig
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