1,720,987 research outputs found
Asynchronous vs Synchronous Input-Queued Switches
Full text linkInput-queued (IQ) switches are one of the reference architectures for the design of high-speed packet switches. Classical results in this field refer to the scenario in which the whole switch transfers the packets in a synchronous fashion, in phase with a sequence of fixed-size timeslots, tailored to transport a minimum-size packet. However, for switches with large number of ports and high bandwidth, maintaining an accurate global synchronization and transferring all the packets in a synchronous fashion is becoming more and more challenging. Furthermore, variable size packets (as in the traffic present in the Internet) require rather complex segmentation and reassembly processes and some switching capacity is wasted due to partial filling of timeslots. Thus, we consider a switch able to natively transfer packets in an asynchronous fashion thanks to a simple and distributed packet scheduler. We investigate the performance of asynchronous IQ switches with different queueing architectures (one queue per input and one queue for input-output pairs) and show that, despite their simplicity, their performance is comparable or even better than those of synchronous switches. We highlight the peculiar role of the variation coefficient of the packet length. Finally, for synchronous switches we evaluate the actual bandwidth overhead due to packet segmentation, by considering a large set of traffic traces covering the period 2008-2013. We show that an impressive amount of bandwidth (up to 30%) can be lost due to segmentation, even if the internal cell size is optimally chosen. These results demonstrate the potential interest of the asynchronous approach in the design of high-performance switche
Multi-MetaRing fairness control in a WDM folded-bus architecture
Full text linkThe paper deals with fairness issues in a slotted, single-hop, WDM (Wavelength Division Multiplexing) optical architecture, based on a folded bus topology, previously proposed as a broadband access system or as a metro network. The peculiar fairness problem arising in this folded bus based architecture is addressed and an extension of the MetaRing protocol to the WDM scenario, named Multi-MetaRing, is proposed. Feasible Multi-MetaRing strategies are defined and analyzed. Both fair access and high aggregate network throughput can be achieved with a low complexity distributed access protocol by properly handling node access through all WDM channel
Short-term Fairness in Slotted WDM Rings
Full text linkSingle-hop WDM ring networks are promising architectures for future broadband access and metro networks. However, ring networks exhibit significant fairness issues, which must be handled by a fairness enforcing protocol. Fairness is usually ensured over a time window of several network propagation delays. Thus, data flows might experience large access delays which might be not compatible to support time-sensitive applications. We solve this issue proposing the Multi-Fasnet protocol, which is able to enforce fairness in a relative short time scale, in the order of few propagation delays, without trading off the aggregated throughput network performance. We discuss Multi-Fasnet limitations and propose several novel strategies that achieve high and fair network throughput as well as low, bounded and fair access delay
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