1,721,119 research outputs found
A sub-1 v nanopower temperature-compensated sub-threshold CMOS voltage reference with 0.065%/V line sensitivity
No full textWe present the design of a nanopower sub-threshold CMOS voltage reference and the measurements performed over a set of more than 70 samples fabricated in 0.18 μm CMOS technology. The circuit provides a temperature-compensated reference voltage of 259 mV with an extremely low line sensitivity of only 0.065% at the price of a less effective temperature compensation. The voltage reference properly works with a supply voltage down to 0.6 V and with a power dissipation of only 22.3 nW. Very similar performance has been obtained with and without the inclusion of the start-up circuit
A Sub-kT/q Voltage Reference Operating at 150 mV
Full text linkWe propose a subthreshold CMOS voltage reference operating with a minimum supply voltage of only 150 mV, which is three times lower than the minimum value presently reported in the literature. The generated reference voltage is only 17.69 mV. This result has been achieved by introducing a temperature compensation technique that does not require the drain-source voltage of each MOSFET to be larger than 4kT/q. The implemented solution consists in two transistors voltage reference with two MOSFETs of the same threshold-type and exploits the dependence of the threshold voltage on transistor size. Measurements performed over a large sample population of 60 chips from two separate batches show a standard deviation of only 0.29 mV. The mean variation of the reference voltage for VDD ranging from 0.15 to 1.8 V is 359.5 μV/V, whereas the mean variation of VREF in the temperature range from 0°C to 120°C is 26.74 μV/°C. The mean power consumption at 25 °C for VDD = 0.15 V is 26.1 pW. The occupied area is 1200 μm2
Experimental Study of Leakage-Delay Trade-off in Germanium pMOSFETs for Logic Circuits
No full textIn this work we explore the potential of the emerging Germanium technology for logic circuits. We introduce an innovative methodology that extracts the main circuit parameters of interest from experimental measurements on 125 nm high k metal gate Ge pMOSFETs in a Si compatible process flow. Appropriate figures of merit are adopted to highlight the potential of Germanium MOSFETs under realistic VLSI designs that fully exploit system level schemes to minimize leakage (e. g., body biasing, stack forcing). On the one hand, Ge devices outperform Si devices in terms of speed due to the higher hole mobility. On the other hand, the higher off state drain current, evaluated ignoring the junction leakage, in Ge pMOSFETs causes an higher standby power dissipation. We show how this drawback can be alleviated by the application of back biasing and stack effect techniques which are intrinsically more effective in Ge devices. In addition, analysis shows that Ge circuits can actually exhibit a 6.4X lower leakage than Si devices, if the threshold voltage is tuned to match the speed of Si devices
Observation of hot-carrier-induced nFET gate-oxide breakdown in dynamically stressed CMOS circuits
No full textVariability-Aware Analysis of Hybrid MTJ/CMOS Circuits by a Micromagnetic-Based Simulation Framework
No full textMagnetic tunnel junctions (MTJs) are attracting an increasing interest due to their potentiality for high-density nonvolatile memories. However, some issues need to be opportunely considered in the design and optimization of hybrid MTJ/CMOS circuits, such as the stochastic nature of the MTJ switching, the high write energy consumption and the susceptibility to process variations. In this paper, we evaluate the impact of both MTJ and CMOS variability on the performance of basic hybrid MTJ/CMOS circuits in state-of-the-art nanoscale technologies. To this purpose, we exploit a simulation framework combining micromagnetic and electrical simulations. Full micromagnetic simulations are used to predict the MTJ behavior in terms of magnetoresistance-current hysteresis loop and statistical distribution of the switching delay as a function of the applied current. Those data are used to set up a look-up-table-based MTJ Verilog-A model to be used in commercial electrical simulators. Considering an MTJ with a diameter of 30 nm and a 28-nm fully-depleted silicon-on-insulator CMOS technology, we have exploited the above simulation framework to perform a variability-aware analysis on the write operation of a 1-MTJ writing circuit for nonvolatile flip-flops and a 256 x 256 STT-MRAM array. Our results show that the voltage scaling can be a promising approach for energy minimization in hybrid MTJ/CMOS circuits at the expense of larger area
STT-MTJ Based Smart Implication for Energy-Efficient Logic-in-Memory Computing
No full textSpin-transfer torque magnetic tunnel junction (STT-MTJ) technology is an attractive solution for designing non-volatile Logic-in-Memory (LIM) architectures. This work explores a smart material implication (SIMPLY) LIM scheme based on nanoscale STT-MTJs. The SIMPLY architecture is benchmarked against the conventional material implication (IMPLY) logic. Obtained results prove that for similar performance the STT-MTJ based SIMPLY scheme ensures more reliable operation (i.e., lower error rate by more than three orders of magnitude) and an energy saving of -70% than its IMPLY counterpart, at the only cost of minimal area overhead
Impact of High-Mobility Materials on the Performance of Near- and Sub-Threshold CMOS Logic Circuits
No full textThis paper studies the impact of high-mobility materials on the performance and energy efficiency of near-and subthreshold CMOS logic circuits by means of analytical equations and experimental data on SiGe pMOSFETs. The introduction of high-mobility materials is shown to improve the energy-performance trade-off in near-threshold circuits more than in above-threshold circuits, since the benefits of higher mobility are degraded at higher longitudinal and transversal electric fields. On the other hand, results show that high-mobility materials do not exhibit any advantage in terms of the energy-performance trade-off in sub-threshold logic circuits. This is explained by the fact that the benefits brought by the larger mobility of SiGe or other alternative materials can be obtained by tuning the threshold voltage of conventional Si devices
Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits
Full text linkIn this work, a complementary InAs/Al0.05Ga0.95Sb
tunnel field-effect-transistor (TFET) virtual technology platform
is benchmarked against the projection to the CMOS FinFET
10-nm node, by means of device and basic circuit simulations.
The comparison is performed in the ultralow voltage regime
(below 500 mV), where the proposed III–V TFETs feature
ON-current levels comparable to scaled FinFETs, for the same
low-operating-power OFF-current. Due to the asymmetrical
n- and p-type I–Vs, trends of noise margins and performances
are investigated for different Wp/Wn ratios. Implications of the
device threshold voltage variability, which turned out to be
dramatic for steep slope TFETs, are also addressed
Novel characterization tool for the study of dielectric breakdown of ultra-thin oxide MOS structures
No full textDielectric breakdown of ultra-thin oxide MOS structures of integrated circuits is preceded by a precursory stage characterized by random on-off fluctuations of the current tunneling through the oxide. In this paper, a new version of a low noise measurement system capable of monitoring these phenomena in a band of 1 kHz is presented. The instrument, controlled by a Personal Computer which stores and elaborates the acquired data, is capable of recognizing the current fluctuations announcing the proximity of the breakdown, so allowing the interruption of the test just a few seconds before the destruction of the sample. Some preliminary observations, made possible by the use of this new analysis tool, are presented in the paper
An Ultralow-Voltage Energy-Efficient Level Shifter
Full text linkThis brief presents an energy-efficient level shifter (LS) able to convert extremely low level input voltages to the nominal voltage domain. To obtain low static power consumption, the proposed architecture is based on the single-stage differential-cascode-voltage-switch scheme. Moreover, it exploits self-adapting pull-up networks to increase the switching speed and to reduce the dynamic energy consumption, while a split input inverting buffer is used as the output stage to further improve energy efficiency. When implemented in a commercial 180-nm CMOS process, the proposed design can up-convert from the deep subthreshold regime (sub-100 mV) to the nominal supply voltage (1.8 V). For the target voltage level conversion from 0.4 to 1.8 V, our LS exhibits an average propagation delay of 31.7 ns, an average static power of less than 60 pW, and an energy per transition of 173 fJ, as experimentally measured across the test chips
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