238 research outputs found
Runtime resource management for lifetime extension in multi-core systems
No full textThe availability of numerous, possibly heterogeneous, processing resources in multi-core systems allows one to exploit them to optimize performance and/or power/energy consumption. In particular, strategies have been defined to map and schedule tasks on the system resources, with the aim of optimizing the adopted figure of merit, at design time, if the working context is known in advance and relatively stable, at run time when facing changing/unpredictable working conditions. However, it is important to be aware that such strategies may have an impact on the overall lifetime of the system because of aging and wear-out mechanisms. Therefore such management strategies, generally adopted for handling performance and power consumption aspects, should be enhanced in order to consider such issues. Furthermore, specific Dynamic Reliability Management (DRM) policies have been devised to deal with lifetime issues in multi-core systems, acting mainly on the workload distribution (and eventually on architectural knobs, such as voltage/frequency scaling) to mitigate the stress caused by the running applications. Here we will focus on DRM strategies, whose goal is pursuing the improvement of lifetime reliability by means of load distribution policies that identify the resource where to map a new application entering the system, or where to periodically migrate tasks to balance stress. More precisely, a selection of state-of-the-art solutions will be presented and analysed, with respect to the achieved expected lifetime, evaluated when considering the first failure as well as the sequence of failures leading to the system being unable to fulfill the user's performance of service requirements
A Software Methodology for Detecting Hardware Faults in VLIW Data Paths
No full textThe proposed methodology aims to achieve processor data paths for VLIW architectures able to autonomously detect transient and permanent hardware faults while executing their ap- plications. The approach, carried out on the compiled application software, provides the introduction of additional instructions for controlling the correctness of the computation with respect to fail- ures in one of the data path functional units. The advantage of a software approach to hardware fault detection is interesting be- cause it allows one to apply it only to the critical applications ex- ecuted on the VLIW architecture, thus not causing a delay in the execution of noncritical tasks. Furthermore, by exploiting the in- trinsic redundancy of this class of architectures no hardware modi- fication is required on the data path so that no processor customiza- tion is necessary
CASTOR: a computer aided system testability optimizer
No full textCASTOR is an expert module that solves testability problems detected in a hardware design by advising the designer on the application of Design for Testabilily techniques. The system evaluates all possible solutions and implements the most economic one in terms of overheads. The optimal solution is obtained by applying a Branch and Bound strategy to carry out the exhaustive search of the best solution, optimizing system resources. A suitable cost function is used to quantify the effects of the application of each DfT technique to the circuit examined
Microelettronica analogica, digitale, Informatica, Telecomunicazioni, Calcolatori digitali
No full textFiltering mobile data by means of context: a methodology
No full textThe goal of this paper is the introduction of a methodol- ogy for designing context-aware data selection for portable devices, where computation, memory, power and connectivity resources are limited, and thus, the possibility to tailor the available, usually too rich, data according to context is a mandatory task. First of all, we will introduce the concept of context and its model, a data structure that expresses knowledge on the user, the environment and the pos- sible scenarios. We will then focus on the proposed methodology for selecting, by means of such information, the relevant data to be made available on a user device. An overall picture of the complete scenario for this context-aware data design and tailoring system will be also provided
Machine learning-based techniques for incremental functional diagnosis: A comparative analysis
No full textIncremental functional diagnosis is the process of iteratively selecting a test, executing it and based on the collected outcome deciding either to execute one more test or to stop the process since a faulty candidate component can be identified. The aim is to minimise the cost and the duration of the diagnosis process. In this paper we compare six engines based on machine learning techniques for driving the diagnosis. The comparison has been carried out under a twofold point of view: on the one hand, we analysed the issues related to the use of the considered techniques for the design of incremental diagnosis engines; on the other hand, we carried out a set of experiments on three synthetic but realistic scenarios to assess accuracy and efficiency
Guest Editors’ Introduction: Special Section on System-Level Design of Reliable Architectures
No full textFault Classification for SRAM-Based FPGAs in theSpace Environment for Fault Mitigation
No full textThis letter proposes a classification algorithm to discriminate between recoverable and not recoverable faults occurring in static random access memory (SRAM)-based field-programmable gate arrays (FPGAs), with the final aim of devising a methodology to enable the exploitation of these devices also in space applications, typically characterized by long mission times, where permanent faults become an issue. By starting from a characterization of the radiation effects and aging mechanisms, we define a controller able to classify such faults and consequently to apply the appropriate mitigation strategy
An output/state encoding for self-checking finite state machine
No full textA new methodology for defining self-checking sequential architectures is presented in the paper. A m-out-of-n encoding of the juxtaposition of next-state and output eventually completed with additional output lines, is provided. The goal is guaranteeing detection of single and multiple unidirectional errors while minimizing area overhead
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