355 research outputs found
A Cache-aware program transformation technique suitable for embedded systems
No full textIn embedded systems caches are very precious for keeping low the memory bandwidth and to allow employing slow and narrow off-chip devices. Conversely, the power and die size resources consumed by the cache force the embedded system designers to use small and simple cache memories. This kind of caches can experience poor performance because of their not flexible placement policy. In this scenario, a big fraction of the misses can originate from the mismatch between the cache behavior and the memory accesses' locality features (conflict misses). In this paper we analyze the conflict miss phenomenon and define a cache utilization measure. Then we propose an object level Cache Aware allocation Technique (CAT) to transform the application to fit the cache structure, minimize the number of conflict misses and maximize cache exploitation. The solution transforms the program layout using the standard functionalities of a linker. The CAT approach allowed the considered applications to deliver the same performance on two times and sometimes four times smaller caches. Moreover the CAT improved programs on direct-mapped caches outperformed the original versions on set-associative caches. In this way, the results highlight that our approach can help embedded system designers to meet the system requirements with smaller and simpler cache memories. (C) 2002 Elsevier Science B.V. All rights reserved
An Educational Environment for Designing and Performance Tuning of Embedded Systems
No full textTeaching how to design and tune an embedded system is indeed a difficult task, since the student has to learn the many trade-offs that lead to the final system configuration. Existing tools are often too complex, or do not stress the basic steps in the design path. These steps are very useful during the first training sessions. The environment Csim2, which is used at our university, permits the student to become familiar with concepts of pro-gram locality, cache structure and performance tuning, while analyzing actual data produced by the actual software that has to be tied with the embedded system. The student can analyze program behavior by means of locality graphs, or run extensive parametric simulations in order to find the best configuration that minimize either sys-tem cost, power consumption, or execution time. Further op-timizations allow the designer to explore more sophisticated features like selective cacheing, cache locking, scratch memory, and code mapping for better cache exploitation. In this paper we show the basic capabilities of the environment, and some example of training sessions. By means of graphs about program locality and performance metric
Social and Q&A interfaces for app download
No full textDownloading software via Web is a major solution for publishers to deliver their software products. In this context, user interfaces for software downloading play a key role. Actually, they have to allow usable interactions as well as support users in taking conscious and coherent decisions about whether to accept to download a software product or not. This paper presents different design alternatives for software download interfaces, i.e. the interface that prompts the user if he wishes to actually complete its download, and evaluates their ability to improve the quality of user interactions while reducing errors in user decisions. More precisely, we compare Authenticode, the leading software download interface for Internet Explorer, to Question-&-Answer, a software download interface previously proposed by the authors Dini, Foglia, Prete, & Zanda (2007). Furthermore, we evaluate the effect of extending both interfaces by means of a reputation system similar to the eBay Feedback Forum. The results of the usability studies show that (i) the pure Question-&-Answer interface is the most effective in minimizing users incoherent behaviors, and (ii) the differences in reputation rankings significantly influence users. Overall results suggest guidelines to design the best interface depending on the context (brand reputation and product features)
DISDEB: an interactive high-level debugging system for a multi-microprocessor system
No full textThis paper describes the architecture of the interactive debugging system DISDEB, which is intended to debug programs on a multi-microprocessor system constituting a node of the Selenia Mara architecture. DISDEB requires neither changes in or additions to the code produced by the compiler nor heavy modifications to the operating system Kernel. Moreover, the use of ad hoc hardware provided with autonomous processing power allows the user to monitor and control the execution of both concurrent and distributed processes and their interactions, while, in most cases, maintaining the real-time operation of the target Mara system
Behavior investigation of concurrent Java programs: an approach based on source-code instrumentation
No full textJava makes easier the coding phase of concurrent applications and provides friendly mechanisms for the information exchange among threads and different processes. The nature of communication and synchronization mechanisms and the actual parallelism of a distributed environment introduce potential sources of non-deterministic behavior in concurrent applications. In order to investigate on undesired effects related to non-deterministic behaviors, tracing and replay capabilities can be added to the programming environment. Such capabilities are useful for testing, debugging, monitoring, performance evaluation and program profiling purposes. This paper presents a solution for providing tracing and replay capabilities to a number of Java concurrent applications. Such a solution addresses portability and it is based on the automatic instrumentation of the original source code. Some transformation schemes have been applied to some classes in the standard Java packages in order to make easier and more efficient the automatic instrumentation task. It is shown how the object-oriented structure of Java can be exploited in a deep and efficient way both in the instrumentation and in the tracing and replay phases. (C) 2001 Elsevier Science B.V. All rights reserved
PSCR: A coherence protocol for eliminating passive sharing in shared-bus shared-memory multiprocessors
No full textIn high-performance general-purpose workstations and servers, the workload can be typically constituted of both sequential and parallel applications. Shared-bus shared-memory multiprocessor can be used to speed-up the execution of such workload. In this environment, the scheduler takes care of the load balancing by allocating a ready process on the first available processor, thus producing process migration. Process migration and the persistence of private data into different caches produce an undesired sharing, named passive sharing. The copies due to passive sharing produce useless coherence traffic on the bus and coping with such a problem may represent a challenging design problem for these machines. Many protocols use smart solutions to limit the overhead to maintain coherence among shared copies. None of these studies treats passive-sharing directly, although some indirect effect is present while dealing with the other kinds of sharing. Affinity scheduling can alleviate this problem, but this technique does not adapt to all load conditions, especially when the effects of migration are massive. We present a simple coherence protocol that eliminates passive sharing using information from the compiler that is normally available in operating system kernels. We evaluate the performance of this protocol and compare it against other solutions proposed in the literature by means of enhanced trace-driven simulation. We evaluate the complexity in terms of the number of protocol states, additional bus lines, and required software support. Our protocol further limits the coherence-maintaining overhead by using information about access patterns to shared data exhibited in parallel applications
Optimizing the Instruction Cache Performance of Embedded Systems
No full textIn the embedded domain, the gap between memory and processor performance and the increase in application complexity need to be supported without wasting precious system resources: die size, power, etc. For these reasons, effective exploitation of small and simple cache memories is of the utmost importance. However, programs running on such caches can experience serious inefficiencies due to cache conflicts.We present a new Cache-Aware Code Allocation Technique (CAT), which transforms the structure of programs so that their behavior toward memory can meet the locality features the cache is able to exploit. The proposed approach uses detailed information of program execution to place program areas into memory and employs the new idea of “look-forward estimation” that helps to seek better global layouts during the placement of each area. CAT-optimized programs outperform the original ones achieving the same miss rate on two times, and sometimes four times, smaller caches. Moreover, CAT improves the instruction miss rate by more than 40% if compared to the best procedure-reordering algorithm. CAT performances derive from the increased number of cache lines that support the execution of optimized applications and from a more balanced load on them
Instrumentation of Concurrent Java Applications for Program Behavior Investigation
No full textJava makes easier the coding phase of concurrent applications and provides friendly mechanisms for the information exchange among threads and different processes. The nature of communication and synchronization mechanisms and the actual parallelism of a distributed environment introduce potential sources of non-deterministic behavior in concurrent applications. In order to investigate on undesired effects related to non-deterministic behaviors, tracing and replay capabilities can be added to the programming environment. Such capabilities are useful for testing, debugging, monitoring and performance evaluation purposes. This paper presents a solution for providing tracing and replay capabilities to Java concurrent applications. Such a solution addresses portability and it is based on the automatic instrumentation of the original source code. Some transformation schemes have been applied to some classes in the standard Java packages in order to make easier and more efficient the automatic instrumentation task. It is shown how the object-oriented structure of Java can be exploited in a deep and efficient way both in the instrumentation and in the tracing and replay phases
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