1,720,994 research outputs found
A Closed-Form Expression of the Drain Current of Asymmetric Double-Gate OTFTs
No full textA continuous, physically based, and analytic current-voltage ( I - V) model of asymmetric independent double-gate organic thin-film transistors is presented. The model is worked out from a closed-form solution of Poisson's equation. A fully analytical expression of interface potentials, accumulation charges, and charge carriers, valid in all the regimes of operations, is derived. Charges and potentials are computed by means of a single nonlinear equation that ensures a natural transition between the hyperbolic and trigonometric modes. The drain current is based on the variable-range hopping and accounts for all the regions of operation. The model is validated by comparisons with the full numerical solution and a very good agreement is shown
A Second-Order Surface Potential Core Model for Submicron MOSFETs
No full textWith the maturity of CMOS technologies and their use in low-voltage analog applications, the accuracy of SPICE models is very important. Here, an extremely accurate yet simple form of the charge-sheet model is developed using a symmetric polynomial interpolation of the charge in the channel. This formulation of the drain current retains the same simplicity of the industry-standard surface potential MOSFET models based on the symmetric linearization method (SLM). But, unlike the SLM, it is developed without requiring the linearization of the charge in the channel, hence, the asymmetries and the nonlinearity are accurately accounted for. The model, although more accurate, has the same computational efficiency and easy implementation of the SLM. Finally, the equations of the currents and terminal charges can be worked out to have the same mathematical form as the SLM
Bipolar Static Induction Transistor With Insulated Gate
No full textIn this article, we show a simple power device architecture that combines the features of the SIT and the power MOSFET: insulated gate, positive threshold, fast switching, current deep in the semiconductor, and compact design. It has the conduction characteristics of a BSIT, and it is voltage-controlled as a MOSFET. Since the large part of the current is not confined at the semiconductor/insulator interface, we believe that it is a promising structure to take advantage of wide bandgap semiconductors that, despite the high mobility and breakdown voltage, still lack high-quality oxide-semiconductor interfaces. The device architecture is devised by means of device simulation both in static and dynamic conditions
A unified core model of double-gate and surrounding-gate MOSFETs for circuit simulation
Full text linkThis paper presents a new core compact model of double-gate (DGFET) and surrounding-gate (SGFET) MOSFETs for circuit simulations. The current and the terminal charges are continuous with high computation efficiency and accuracy. Despite its accuracy, it retains the same simplicity of the industry standard transistors models. The drain current is worked out without invoking the charge-sheet approximation exploiting a quadratic symmetric polynomial interpolation of the charge in the channel. Apart this clear approximation, no other simplification is used to work out the drain current, the terminal charges, the potential, and electric field in the channel. The accuracy of the model is shown by comparison with the exact numerical solution and experimental data of the literature
PSP-Equivalent Model for Double-Gate and Surrounding-Gate Field Effect Transistors for Circuit Simulation
Full text linkWe introduce a compact core model for double-gate (DGFET) and surrounding-gate (SGFET) MOSFETs designed for circuit simulations. Despite its high precision, the model is crafted to retain the same analytic formulation of the industry standard Pennsylvania State and Philips (PSP). Instead of linearizing the drain current as in the PSP model, we employ a quadratic symmetric polynomial interpolation of the charge in the channel. This eliminates the need for cumbersome derivatives, simplifications, and intricate coding when integrating into a circuit simulator, thereby preventing singularities during numerical iterations. Moreover, thanks to its mathematical formulation equivalent to PSP, this model simplifies the coding of terminal charges, capacitances, potentials, and electric fields in the channel within circuit simulators. We validate the accuracy of the model through comparisons with numerical solutions and experiments from the literature
Increasing EMI Immunity and Linearity of a CMOS 180 nm Voltage-to-Delay Converter
No full textThis paper presents a voltage-controlled delay unit (VCDU) with a novel architecture allowing for a wide input range of linearity and an improved immunity to electromagnetic interferences. The circuit is based on a current-starved inverter with a biasing technique to extend the input voltage range of linearity near to the rail-to-rail linearity range. The proposed scheme was designed by UMC 180 nm standard CMOS process and works without power-hungry amplifiers or comparators. It has a voltage supply of 1.8 V and exhibits a rail-to-rail linearity range (0–1.8 V) with an average EMI-induced jitter of only 1% of the nominal delay
A review of fully integrated and embedded power converters for IoT
No full textThe Internet of Things (IoT) has found application in many components of implantable medical devices, wearable smart devices, monitoring systems, etc. The IoT devices are conventionally battery powered, even though, in several low power applications, they can also be powered using energy harvesting technology. Independently of the power sources (if batteries or environment), efficient and robust power converters must be designed to provide the small and distributed energy required by such IoT devices. This review paper will first provide an overview about the power consumption in IoT devices; second, it will discuss the most recent research and advance in the field of fully-integrated or embedded DC/DC converters, starting from high-performance integrated charge pumps or embedded inductive boost converters for specific harvesting sources (temperature, solar, and so on), to novel DC/DC converters for multiple energy sources
EMI Effect in Voltage-to-Time Converters
No full textThis letter presents the effects of electromagnetic interferences in the Voltage-to-Time Converters (VTC), one of the most important circuits in Time-Mode Signal Processing. The VTC is based on two Voltage-Controlled Delay Units; it is designed in a standard 180nm CMOS technology and it is exposed to the electromagnetic interferences, picked up from the I/O pins and the power supply rails. The VTC circuits are susceptible to the interferences which can cause timing jitter and non linearity. It is found that the level of the susceptibility depends on the amplitude of the interferences, on their frequency and also on their initial phase
EMI susceptibility of the output pin in CMOS amplifiers
No full textMeasurements in commercial devices demonstrate a considerable susceptibility of the operational amplifiers to the electromagnetic interferences coupled to their output pin. This paper investigates some basic architectures starting from single stage amplifiers up to a whole operational amplifier. The result is a correlation between the different amplifier configurations, the output impedance and the susceptibility to the interferences. The simulations are perfomed by using the standard CMOS UMC 180nm technology and by running the netlist of the schematics extracted from the layout
Increasing the Immunity to Electromagnetic Interferences of CMOS OpAmps
No full textThis paper presents the successful design of a CMOS operational amplifier with enhanced immunity to electromagnetic interferences. Thanks to its strongly symmetrical topology, the amplifier exhibits an intrinsic robustness to interferences arising from a wide class of sources. Such a scheme, for the first time in the authors' knowledge, proves the effectiveness of symmetrical topologies to minimize the effects of electromagnetic interferences in operational amplifiers. The amplifier architecture is based on 2 identical stages: 2 fully differential source cross-coupled amplifiers with active loads. The circuit was fabricated in a 0.8 μm n-well CMOS technology (AMS CYE process). Experimental results, in terms of EMI immunity, are presented and compared with a commercial amplifier. They show a low susceptibility to EMI conveyed both to the input and the power pins. The EMI effects on the proposed amplifier are reduced by more than one order of magnitude, compared to a commercial amplifier. Furthermore the amplifier overall measured performances are provided along with the corresponding simulation results
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