329,752 research outputs found
CLASS, CONSUMPTION, AND LIFESTYLES IN URUGUAY
No full textThe advance of neoliberalism in the last quarter of the twentieth century transformed the material culture of Latin American societies. Consumerism became a prominent means of expressing and realizing citizen’s rights and freedoms. As the commodification of material life gains importance, the patterns of class differentiation are expected to revolve, increasingly, around consumption. In this thesis, I examine the classic sociological proposition that consumption plays a fundamental role in the making of differentiating lifestyles, and that such lifestyles delimit and reinforce social class cleavages. From this perspective, I study the statistical relations between social structure and consumption, determining the extent to which class differences account for variation in a set of consumption patterns inferred from the National Survey of Household Expenditures and Incomes conducted in Uruguay in 2005/2006. I pick a set of food and non-food items and use Multiple Correspondence Analysis to assess how the acquisition of specific goods and services cluster along different dimensions and thus reveal different consumption patterns. For food consumption, I identify a first dimension expressing the distinction between a diversified and good quality diet, and a restricted and lower quality diet. A second dimension revolves around the acquisition of calorific and “filling” food. For non-food consumption, the first principal dimension makes the difference between the possession or not of omnivorous tastes / positional goods, while the second dimension distinguishes between the quest for an aesthetic / outward oriented lifestyle and a comfort-seeking / inward oriented lifestyle. To test class effects on these consumption patterns, I fit a set of linear regression models, using the predicted scores derived from MCA as dependent variables. I confirm that 1) there is an overall class effect on consumption patterns, 2) both income and education mediate such an effect, and 3) there is a specific class effect on consumption that is not reducible to the effect of purchasing power and educational attainment
The interferences of Class-D amplifiers with AM/FM and their eliminations
No full text碩士Class-D放大器(D類放大器)衍生的目的在於改善及提升AB類放大器(Class-AB)的特性，簡述如下：
1. 效能提升，可達>85%(傳統的AB類放大器效能僅為50%)。
2. 降低散熱片的倚賴性，甚至在低功率(20W以下)時可完全將散熱片捨棄，因此商業用途的產品體積即可縮小，如：手機、PMP等。
3. 但同時也造成另一個問題的出現：EMI的干擾。
簡單說，Class-D放大器內部電路的設計方式是將原始的類比信號波形，與比它更高頻率的三角波（或鋸齒波）進行電壓比較（透過電壓比較器），如此便可將以振幅高低性表示的信號調變成以脈波寬窄性表示的信號，此即是脈寬調變（Pulse Width Modulation；PWM），之後將PWM信號輸出到MOSFET場效電晶體上的閘極，以控制電晶體的導通、關閉(簡稱：開關頻率)，同時也在這個階段進行信號功率放大，最後MOSFET的輸出端連接LC（電感、電容）低通濾波電路，將PWM的載波濾除，使原始信號波形重新呈現。
因此，此份研究報告的內容將針對Class-D放大器對AM/FM的干擾與排除進行研究與分析。究其干擾原因，CLASS-D放大器的開關訊號會經由低通濾波器的電感輻射出去，對調幅(AM/FM)廣播產生干擾，被干擾的電台主要是位在CLASS-D放大器開關頻率的諧波上。如原本的開關頻率是300KHz， 則在其倍數頻率上的電台(600KHz、900KHz、1200KHz、1500KHz)通通會被影響，主要症狀是倍頻處的電台接收靈敏度突然變差或遭受到蓋台。因此，研究的重點在於干擾的產生及如何排除的方式，其概念如下簡述：原理是產生一個外部的基準時脈給Class-D放大器，利用IC內部PWM開關頻率的改變抑止倍頻干擾而產生的問題。如：干擾AM電台問題，將設有兩個震盪頻率可供選擇(430KHz與480KHz)，在接收不同電台時可以切換系統震盪頻率來避掉干擾. 一般當接收電台的頻率位在CLASS-D放大器開關頻率倍頻的±30KHz以內時就可以更換系統主震盪頻率，每次只有一個震盪器在工作，頻率的選擇由外部電路來決定，以解決倍頻的干擾。FM的干擾解決方式採用金屬材質的外殼屏蔽，以便衰減諧波輻射的干擾能量，進而使得FM接收正常。Only the power amplification of A, B, mostly used in the amplifier of audio systems had learned in school. And most consumer audio and public announcement systems use Class-AB topology today. However how is Class D developed?
In fact, D amplifier (Class-D) is to improve and promote the performance of AB amplifier (Class-AB), and short depictions as followed:
1. Increasing efficiency, can reach > 85% (the traditional Class-AB amplifier is only 50% efficient.)
2. Decreasing the dependence of the heat sink, even in the low power (under 20W) the heat sink is not required, so the size of products for the commercial uses can be diminished, for instance: Mobile phone, PMP, etc.
3. But it could cause another problem at the same time: interference with EMI.
Briefly, the design of Class-D’s circuits is to compare the original analog signal waveform with triangular waveform or sawtooth waveform operated at the high frequency. So that the voltage level of signal transmits to the pulse width, this is so called Pulse Width Modulation; PWM. Then PWM transmits to the transistor of MOSFET to control the switch of transistor (short for: Switching Frequency), at the same time power is amplified. Finally the output connecting MOSFET of LC (inductance, capacitor) drives through low pass circuits and filters through the carrier wave to reveal the original wave of single again.
Therefore this is the research of interfere with AM/FM and elimination by Class D.
The cause of interference is that the switch signal of Class-D will go out via the low pass inductance radiation and then Class-D is interfered with the amplitude modulation (AM/FM). The radio station interfered is on the distortion waves of the switch frequency. If the original signal having a switch frequency of 300 KHz, for example, the radio stations broadcasting on the multiple frequency (600 KHz,900 KHz,1200 KHz,1500 KHz) are affected. The main symptoms are that the delicacy of receiving the signal by the radio station becomes weak suddenly or one radio station is covered with the other one.
Thus, the key point of this research is finding out the methods to avoid from interference and estimations. The concept is stated as below. To install an outside basic clock in Class-D and use the change of the switch frequency of PWM to avoid the interference with multiple frequency. Take the interference with AM for example; there are two choices of basic clocks (430 KHz and 480 KHz). The way to avoid interference is by exchanging frequency automatically. Generally the system will change the basic clock to a tolerance of +/- 30 KHz. There is always one basic clock operated. The choice of frequency will depend on the outside circuits in order to solve the problem of multiple frequencies.第一章 緒論 1
1.1 研究動機 1
1.2 Class-D放大器的演化過程 3
1.2.1 Class-AB放大器與Class-D放大器之兩者主要差異 3
1.2.2 A類功率放大器之介紹 4
1.2.3 B類功率放大器之介紹 6
1.2.4 AB類功率放大器之介紹 9
第二章 Class-D放大器的內部電路設計架構及原理探討 10
2.1 Class-D放大器之介紹 10
2.2 Class-D放大器之功率效應 12
2.3 Class-D放大器的動作原理 15
2.3.1 Class-D 放大器IC概念 17
2.3.2 Class-D 放大器IC應用電路 19
2.3.3 PWM動作原理 22
2.3.4低通濾波器原理及電路 24
第三章 Class-D放大器對AM/FM的干擾源的產生與分析 29
3.1 Class-D放大器對AM/FM干擾產生的現象29
3.1.1測試架構圖 30
3.1.2 PWM對於AM/FM之干擾概述 31
3.1.3針對干擾源現象之測試模式 31
3.1.4測試後之波形 31
3.2 干擾源產生的原理 36
3.3 對於AM/FM的干擾現象解析 37
第四章 對於倍頻及EMI干擾的排除與模擬實驗結果之探討 40
4.1 排除倍頻/EMI干擾之電路架構及原理解說 40
4.1.1 排除倍頻干擾之應用電路圖(2顆Class-D IC) 40
4.1.2 CLOCK SOURCE SEL實體PCB板 41
4.1.3 排除倍頻干擾之原理解說(AM之干擾解決方法) 41
4.1.4 排除EMI干擾之原理解說(FM之干擾解決方法) 42
4.2 電路模擬實驗結果 43
4.2.1 AM干擾解決方式之實驗結果 43
4.2.2 FM干擾解決方式之實驗結果 50
第五章 結論與未來展望 51
Reference 52
圖目
圖 1.1: A類放大器輸出架構圖 4
圖 1.2: A類放大器的特性曲線 5
圖 1.3: B類放大器輸出架構圖 6
圖 1.4: B類放大器的特性曲線 7
圖 1.5:交越失真造成說明曲線 8
圖1.6：AB類放大器輸出架構圖…………………………………………………………9
圖 2.1:傳統(A、B、AB)類放大器最後一級訊號之關係 11
圖 2.2:數位化-D類放大器最後一級訊號之關係 11
圖 2.3: Class-D放大器之輸出功率示意圖 13
圖 2.4: Class-D放大器內部邏輯電路圖及外部LC之示意圖 16
圖 2.5: Class-D放大器 IC 方塊圖(僅為單聲道示意圖) 17
圖 2.6: Class-D 放大器IC 應用電路圖 19
圖 2.7:無輸入訊號，IC輸出端(低通濾波電路(LC電路)前) 20
圖 2.8:輸入1KHz訊號，輸出端(低通濾波電路(LC電路)前) 20
圖 2.9:輸入1KHz訊號，輸出至喇叭端的音源波形(低通濾波電路(LC電路)後)…. 21
圖 2.10: PWM的輸出波形示意圖…. 23
圖 2.11:低通濾波器的頻率響應…. 25
圖 2.12:特沃斯 (Butterworth)、卻比雪夫(Chebyshev)、貝塞爾(Bessel) 濾波器的特性 曲線…. 26
圖 2.13:二階LC型的巴特沃斯(Butterworth)濾波器…. 26
圖 2.14:實際的BTL電路…. 27
圖 3.1: Class-D放大器 IC應用於汽車音響上的PCB板………………………..…….29
圖 3.2:測試架構圖 30
圖 3.3: AM：Class-D放大器“不動作”時之環境測試 32
圖 3.4: AM：Class-D放大器“動作”時之環境測試，基頻270KHz 32
圖 3.5: AM：Class-D放大器“動作”時之環境測試，二次諧波600KHz 33
圖 3.6: AM：Class-D放大器“動作”時之環境測試，三次諧波900KHz 33
圖 3.7: AM：Class-D放大器“動作”時之環境測試，四次諧波1200KHz 34
圖 3.8: FM：Class-D放大器“不動作”時之環境測試……………………………….. 34
圖 3.9: FM：Class-D放大器“動作”時之環境測試 35
圖 3.10: 關關頻率之波形 36
圖 4.1: AM干擾解決方式之電路圖 40
圖 4.2: CLOCK SOURCE SEL實體PCB板 41
圖 4.3: FM之解決方式 42
圖 4.4: 頻率430KHz時的模擬實驗波形 45
圖 4.5: 頻率480KHz時的模擬實驗波形…………………………………………..…...47圖 4.6: 頻率430KHz與480KHz時的模擬實驗之關係波形…………………………..49
圖 4.7: FM模擬實驗結果的波形 50
表目
表 2.1：對應特定fc和R的電感（L）值和電容（C）值 28
表 3.1: 測試儀器資料 30
表 3.2: AM的頻率表...…………….……....………………………..................................37
表 4.1: AM頻道對主震盪頻率模擬實驗結果之數據關係表….....……….....................43學號: 793350124, 學年度: 9
CMOS Highly-Efficient Class-D Audio Amplifier
No full textA one-chip integrated circuit of a 2-W class-D audio power amplifier with very high efficiency using a CMOS technology is presented. Compared with traditional class-AB amplifiers that are very poor at efficiency, most below 50%, the proposed class-D amplifier has the efficiency of 90% at the smaller distortion level. The class-D amplifiers generate pulse-width-modulated (PWM) signals by comparing a triangle-wave with input-signals. An output stage with zero dead time and high efficiency is applied to improve the linearity and reduce wasted battery energy. An approach to reducing distortion is applied by using feedback calibration.Contents
Acknowledgement…………………………………………………………….. i
Abstract………………………………………………………………………. ii
Contents……………………………………………………………………… iii
Figure Captions………………………………………………………………. v
Table Captions………………………………………………………………viii
Chapter 1 Introduction
Chapter 2 Principle and Design of the Class-D Audio Power Amplifier
2.1 Structure of the Class-D Amplifier 3
2.2 Principle of the pulse 5
2.3 Advance Issues of Class-D Amplifier 8
2.3.1 Design and Distortion of the Output Stage 8
2.3.2 Power Efficiency 13
2.4 Previous Work of the Class-D Amplifier 18
2.4.1 A Class-D Amplifier Using A Spectrum Shaping Technique 18
2.4.2 A 700mW Class-D Design with Direct Battery Hookup in a 90nm Process 19
2.4.3 An Integrated 200W Class-D Audio Amplifier 22
Chapter 3 The Proposed Circuit of The Class-D Audio Power Amplifier
3.1 The Proposed Circuit of The Class-D Audio Power Amplifier and Simulation Result 26
3.2 Structure of the Proposed Class-D Amplifier 28
3.3 Implementation of the Block Diagram 29
3.2.1 Triangle Waveform Generator 29
3.2.2 The PWM Comparator 30
3.2.3 The Integrator of the Input Stage 31
3.2.4 The Nonoverlapping Driving Circuit 32
3.2.5 The Low-pass Filter 33
3.3 Simulation Result for Proposed Circuit 34
3.3.1 Relationship of fin and the Total Harmonic Distortion 34
3.3.1 Power Efficiency 34
Chapter 4 Conclusion
5.1 Conclusions 36
5.2 Future Work 37
Reference 3
Ultra-Low Idle Power Class-D Amplifier
No full textClass-D amplifiers are widely used in automotive audio systems because of their high efficiency. In modern car sound systems, multiple amplifiers are used to provide good audio effect. However, typical class-D amplifiers have a high idle-power, which can drain the battery quickly. To solve this problem, an ultra-low idle power class-D amplifier is proposed in this thesis. The simulation results show that this amplifier can achieve very low idle power while maintaining competitive linearity and efficiency.Electrical Engineering | Microelectronic
D-Class Dreams
No full textD-Class Dreams is a short poem referencing the Derwent Class sailing vessels, much beloved by Hobart maritime enthusiasts of the 20th century
Chopper PWM-Based Class-D Amplifier
No full textClass-D amplifiers are widely used in audio applications that require a high power efficiency. A high PSRR is beneficial when the power supply contains significant audio band content. Due to mismatches present in the feedback, these can dominate the PSRR of the class-D amplifier, provided the amplifier has sufficient loop gain. No literature has been found that describes a solution to improving the PSRR and CMRR across the full audio band. This work proposes chopping of the input and feedback resistors in a class-D to address this issue. With this technique's application, a >100dB PSRR and CMRR across the audio band is achieved
Delta Sigma Modulated Class D Audio Amplifier
No full text在商用的行動電子設備中，電池的續行力是個很重要的問題。現今的行動電話，個人數位助理，數位隨身聽等等。都期望有長時間的電池供應時間。因此電子裝置的功率效率越來越受到重視。
在許多的電子設備中，都有音訊的輸出裝置。傳統上的音訊輸出裝置是由A類輸出級，AB類輸出級或B類輸出級組成。但是傳統的輸出級體積大，功率效率低，而且容易發熱。因此，因應而生的D類輸出級便有了體積小，效率高等等的優點，可以更適用在現今的電子裝置中。
一般的使用D類輸出級之音頻放大器，都採用脈寬調變技術(Pulse Width Modulation)或是三角積分調變(Delta Sigma Modulation)技術。而該兩種調變方式的電路施行中，通常包含一個時脈電路。
本論文提出一使用三角積分器之D類放大器，並在三角積分器之電路施行方式中捨棄時脈電路，採用磁滯比較器取代量化器並得以節省下時脈電路，並仍可達到相當水準之輸出功率效率以及總協波失真。In the portable devices such as PDA, MP3 player or mobile phone and mobile amusement system, the battery life is a very important issue. In order to strengthen the battery lifetime, the high power efficiency will be better.
The efficiency of power amplifier is very important. The traditional class A or class AB have lower efficiency than class D. The efficiency of class D will achieve 100% theoretically.
The class D audio amplifier is usually with PWM modulator or delta sigma modulator to transform the input signal to a series of pulse signal to control the class D circuit. The traditional PWM modulator or delta sigma modulator are all with clock circuit inside. In order to reduce the clock circuit, a delta sigma modulator with hysteresis comparator is presented in this thesis. In this topology, we can save the chip area and also can achieve a good performance in THD and efficiency. The THD is 0.9% and the efficiency is 87% with 10K Hz input signal in this thesis.Chapter 1 Introduction ……………………………………………………1
1.1 Motivation …………………………………………………...1
1.2 Class D amplifier operation ……………………………………1
Chapter 2 Power amplifiers ………………………………………………5
2.1 Linear mode and switch mode power amplifier ………………5
2.2 Type of power amplifier …………………………………………6
2.2.1 Class A amplifier …………………………………………6
2.2.2 Class B amplifier …………………………………... 8
2.2.3 Class AB amplifier …………………………………..12
2.2.4 Class D amplifier ……………………………………….13
Chapter 3 Audio modulators ……………………………………………..16
3.1 PWM modulator ………………………………………………..16
3.2 Delta modulator ………………………………………………...19
3.3 Delta-sigma modulator …………………………………………24
Chapter 4 Circuit design and simulation………………………….29
4.1 Motivation ………………………………………………………29
4.2 System block diagram ………………………………………..29
4.3 Circuit implementation ………………………………………...36
4.3.1 Integrator ……………………………………………..36
4.3.2 Hysteresis comparator ……………………………..40
4.3.3 Class D amplifier …………………………………..45
4.3.4 Class D amplifier and Output filter …………………..47
4.3.5 Simulation results …………………………………..48
Chapter 5 Conclusions …………………………………………………..55
References ………………………………………………………………………..5
Evaluatıon Of The Hyoid Bone Posıtıon In Class I, Class II D 1 And Class III Malocclusıons
No full textComparative examination of the position of the hyoid bone and its relation with dentofacial system according to its position on total of 45 patients with Class I, Class II D1 and Class III malocclusions. SNA, SNB and ANB, Go-Gn-SN angles are used as identification parameters for different malocclusions. 7 horizontal, 5 vertical and 5 angular measurements are evaluated in order to establish the position of the hyoid bone. SN plane is used as the reference plane. Mann-Whitney test is used to evaluate the measurements statistically. When Class I and Class II D 1 groups are compared, statistically significant differences are observed in At-H, H-CVT ,H-OP and A-H, N-H, PTR-H. When Class I and Class III groups are compared statistically significant differences are seen in At-H ve H-OP and A-H, N-H, PTR-H H measurements. In Class II D 1 malocclusion the position of the hyoid bone is found to be more posterior than normal and in Class III malocclusion more anterior than normal
The beat frequency cancellation circuit design of dual channel class d audio power amplifier
No full text碩士音頻功率放大器對於一個音響系統扮演著很重要的角色。但若以功率效益方面來比較，D類功率放大器有較優越的輸出功率表現。對於理想的D類功率放大器而言,它的最大效率理論上是可達到90%甚至100%。
採用自激振盪調制方式的Class D音頻功率放大器IC晶片內部電路設計成可使用在兩個或多個獨立的音效聲道上，在兩聲道功率輸出 PWM 方波訊號會有震盪頻率非同步的情況發生，而產生出所謂差頻的現象，假使其聲音頻率差距在人耳周波數的範圍內，此時IC工作在無音源信號輸出下，就會很容易產生這樣的差頻聲音，雖然聲音微弱但也會很清楚的被人耳所聽到，而造成IC使用上的困擾。
而為了解決這樣的問題，本論文針對雙聲道Class D音頻功率放大器所產生出來的差頻問題而設計出的應用測試電路來做其探討和研究。Audio power amplifiers play an important role in the audio system.Compared by power efficiency,Class-D power amplifiers have better performance.The theoretical maximum efficiency of Class-D designs is 100%,and over 90% is attainable in practice.
Use the self-oscillation Class D audio power amplifiers IC chip''s internal circuit is designed to be used on dual or several multi independent audio channel, and when dual audio channel transmit output power,PWM signal osc frequency is nonsynchronous and result the Beat Frequency. If the difference of sound frequency is within the range for ear''s frequency, IC work tends to occur the situation of the Beat Frequency when there is no sound source''s signal output at this time.
Although the sound is weak, people can still hear it clearly and which will cause persecution when using IC.In order to solve such problem, this theory is aimed at the problem of the Beat Frequency which is caused from dual audio channel Class D and designs the applied test circuit for discuss and study.目錄
中文摘要..I
英文摘要..II
誌謝..III
目錄..IV
圖目..VI
表目..IX
第一章 緒論..1
1.1 Class D音頻功率放大器發展與背景..1
1.2 研究動機..2
1.3 論文架構..3
第二章 音頻功率放大器..4
2.1 音頻功率放大器..4
2.2 A類音頻功率放大器..6
2.3 B類音頻功率放大器..8
2.4 AB類音頻功率放大器..11
第三章 D類音頻功率放大器原理及基本架構..15
3.1 Class D音頻功率放大器介紹..15
3.2 Class D類音頻功率放大器基本原理與架構..16
3.2.1 全橋式架構D類輸出級..21
3.3 D類音頻功率放大器的效率..23
3.4 D類音頻功率放大器的失真..25
3.5 D類音頻功率放大器輸出級保護..26
3.6 D類音頻功率放大器EMI處理和LC低通濾波器..28
第四章 D類音頻功率放大器頻率差消除電路..31
4.1 自激振盪D類音頻功率放大器基本電路架構..31
4.1.1 自激振盪..32
4.2 D類音頻功率放大器自激振盪原理..34
4.3 D類音頻功率放大器頻率差消除電路設計與原理..38
4.4 頻率差消除電路測試分析及研究..46
第五章 應用頻率差消除電路前後量測結果與差異..54
5.1 D類音頻功率放大器之量測..54
5.2 效率(Efficiency)及功率消耗(PD)測試..56
5.3 總諧波失真加雜訊(THD+N)測試..61
5.4 輸出功率(PO)測試..64
5.5 串音分離度(Crosstalk)測試..67
5.6 信號雜音比(SNR)測試..69
5.7 量測D類音頻功率放大器的應用問題..71
第六章 結論..72
6.1 結論..72
6.2 未來展望與研究方向..73
參考文獻..74
圖目錄
圖 2.1 功率放大器基本架構圖..4
圖 2.2 音頻功率放大器方塊圖..5
圖 2.3 A類功率放大器電路..6
圖 2.4 A類功率放大器交直流輸出波形特性曲線圖..6
圖 2.5a 共集極組態..7
圖 2.5b 共射極組態..7
圖 2.6 B類功率放大器電路..8
圖 2.7 B類功率放大器交直流輸出波形特性曲線圖..9
圖 2.8 B類功率放大器轉移特性曲線..10
圖 2.9 B類功率放大器輸出信號交越失真..10
圖 2.10 AB類功率放大器電路..11
圖 2.11 AB類功率放大器對於交越失真的改善情形..12
圖 2.12 AB類功率放大器交直流輸出波形特性曲線圖..12
圖 2.13 AB類功率放大器轉移特性曲線..13
圖 2.14 AB類的工作點..13
圖 3.1 D類功率放大器基本架構方塊圖..16
圖 3.2 PWM基本架構..17
圖 3.3 D類功率放大器電壓波形..18
圖 3.4 D類功率放大器單端系統架構..19
圖 3.5 D類功率放大器雙端系統架構..20
圖 3.6 D類功率放大器死區時間(Dead time Delay)..20
圖 3.7 全橋式架構D類輸出級和LC低通濾波器..21
圖 3.8 全橋式架構D類輸出波形..21
圖 3.9 負載電阻RL與內阻RDS(ON)..24
圖 3.10 D類功率放大器主要失真..25
圖 3.11 典型被動LC低通濾波器..30
圖 4.1 自激振盪方式D類功率放大器的基本電路架構..31
圖 4.2a 自激振盪負反饋方塊圖..32
圖 4.2b 自激振盪電路方塊圖..32
圖 4.3 自激振盪全橋式D類功率放大器的基本電路架構..34
圖 4.4 D 類功率放大器自激振盪架構PWM信號波形..34
圖 4.5 比較器到VOUT端延遲時間..37
圖 4.6 加入延遲後之波形..37
圖 4.7 (VDD=12V)D類功率放大器全橋式差動輸出頻率波形..38
圖 4.8 頻率差消除電路架構圖..39
圖 4.9 差動輸出端狀態示意圖..41
圖 4.10 頻率差消除電路電流與時間變化波形圖..43
圖 4.11 頻率差消除電路ICA與ICB電流波形圖..44
圖 4.12 (VDD=12V，C1、C2=12pF)應用差頻消除電路輸出頻率波形..46
圖 4.13 (VDD=8.5V)D類功率放大器全橋式差動輸出頻率波形..47
圖 4.14 (VDD=8.5V，C1、C2 =12pF)應用差頻消除電路輸出頻率波形..48
圖 4.15 (VDD=15V)D類功率放大器全橋式差動輸出頻率波形..48
圖 4.16 (VDD=15V，C1、C2=12pF)應用差頻消除電路輸出頻率波形..49
圖 4.17 (VDD=8.5V，C1、C2=10pF)應用差頻消除電路輸出頻率波形..50
圖 4.18 (VDD=12V，C1、C2=10pF)應用差頻消除電路輸出頻率波形..50
圖 4.19 (VDD=15V，C1、C2=10pF)應用差頻消除電路輸出頻率波形..51
圖 4.20 (VDD=8.5V，C1、C2=15pF)應用差頻消除電路輸出頻率波形..51
圖 4.21 (VDD=12V，C1、C2=15pF)應用差頻消除電路輸出頻率波形..52
圖 4.22 (VDD=15V，C1、C2=15pF)應用差頻消除電路輸出頻率波形..52
圖 5.1 硬體電路測試儀器Audio Precision音頻分析儀..55
圖 5.2 (RL=4Ω)右聲道功率輸出VS效率變化圖..57
圖 5.3 (RL=4Ω)左聲道功率輸出VS效率變化圖..57
圖 5.4 (RL=8Ω)右聲道功率輸出VS效率變化圖..58
圖 5.5 (RL=8Ω)左聲道功率輸出VS效率變化圖..58
圖 5.6 (RL=4Ω)右聲道功率輸出VS功率消耗變化圖..59
圖 5.7 (RL=4Ω)左聲道功率輸出VS功率消耗變化圖..59
圖 5.8 (RL=8Ω)右聲道功率輸出VS功率消耗變化圖..60
圖 5.9 (RL=8Ω)左聲道功率輸出VS功率消耗變化圖..60
圖 5.10 (RL=4Ω)右聲道PO=1W失真VS頻率曲線圖..62
圖 5.11 (RL=4Ω)左聲道PO=1W失真VS頻率曲線圖..62
圖 5.12 (RL=8Ω)右聲道PO=1W失真VS頻率曲線圖..63
圖 5.13 (RL=8Ω)左聲道PO=1W失真VS頻率曲線圖..63
圖 5.14 (RL=4Ω)右聲道輸出功率VS失真曲線圖..65
圖 5.15 (RL=4Ω)左聲道輸出功率VS失真曲線圖..65
圖 5.16 (RL=8Ω)右聲道輸出功率VS失真曲線圖..66
圖 5.17 (RL=8Ω)左聲道輸出功率VS失真曲線圖..66
圖 5.18 右聲道對左聲道串音分離度VS頻率曲線圖..68
圖 5.19 左聲道對右聲道串音分離度VS頻率曲線圖..68
圖 5.20 右聲道信號雜訊比VS頻率曲線圖..70
圖 5.21 左聲道信號雜訊比VS頻率曲線圖..70
表目錄
表 2.1 各類型放大器優缺點比較表..14
表 4.1 差動輸出端狀態表..41
表 4.2 加入差頻消除電路後量產測試良率數據..53
表 5.1 Class D音頻功率放大器規格表..55學號: 798440193, 學年度: 10
High-Performance Multilevel Class-D Audio Amplifiers
No full textThis thesis describes the analysis, design, prototype implementation, and measurement results of high-performance Class-D amplifiers (CDAs) for audio applications.Electronic Instrumentatio
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