1,721,071 research outputs found
Efficient Bit-Parallel GF(2m) Multiplier for a Large Class of Irreducible Pentanomials
No full textL'articolo descrive una nuova rappresentazione degli elementi nei campi finiti di tipo GF(2^m) che consente la realizzazione di architetture hardware parallele più efficienti e flessibili rispetto ai più recenti contributi presentati nella letteratura tecnica. La rappresentazione trova impiego nella realizzazione di circuiti per operazioni crittografiche, codici per la correzione dell'errore, etc.
SOMMARIO DELL'ARTICOLO:
This work studies efficient bit-parallel multiplication in GF(2^m) for irreducible pentanomials, based on the so-called Shifted Polynomial Bases (SPBs). We derive a closed expression of the reduced SPB product for a class of polynomials x^m+x^(k_s)+ x^(k_(s-1))+... +x^(k_1)+1, with k_s-k_1<= (m+1)/2. Then, we apply the above formulation to the case of pentanomials. The resulting multiplier outperforms, or is as efficient as the best proposals in the technical literature, but it is suitable for a much larger class of pentanomials than those studied so far. Unlike previous works, this property enables the choice of pentanomials optimizing different field operations (for example, inversion), yet preserving an optimal implementation of field multiplication, as discussed and quantitatively proved in the last part of the paper
A New Speculative Addition Architecture Suitable for Two's Complement Operations
No full textL'articolo presenta una innovativa architettura parallela per l'operazione di addizione basata su approccio speculativo. L'architettura introdotta mostra promettenti margini di miglioramento rispetto ad approcci simili recentemente presentati in letteratura, in particolare per quanto riguarda applicazioni con operandi lunghi ed operazioni effettuate su numeri in complementi (a differenza dei lavori precedenti
Exploring the Potential of Threshold Logic for Cryptography-Related Operations
No full textMotivated by the emerging interest in new VLSI processes and technologies, such as Resonant Tunneling Diodes (RTDs), Single-Electron Tunneling (SET), Quantum Cellular Automata (QCA), and Tunneling Phase Logic (TPL), this paper explores the application of the non-Boolean computational paradigms enabled by such new technologies. In particular, we consider Threshold Logic functions, directly implementable as primitive gates in the above mentioned technologies, and study their application to the domain of cryptographic computing. From a theoretical perspective, we present a study on the computational power of linear threshold functions related to modular reduction and multiplication, the central operations in many cryptosystems such as RSA and Elliptic Curve Cryptography. We establish an optimal bound to the delay of a threshold logic circuit implementing Montgomery modular reduction and multiplication. We also propose an architecture for modular reduction and multiplication which ensures feasible O(n^2) area requirements, preserving the properties of constant latency and a low architectural critical path independent of the input size n. We compare this result with several state-of-the-art proposals in the literature based on the Boolean computational model, showing that the presented approach has intrinsically better architectural delay and latency, both O(1), thereby outperforming systolic and fully parallel solutions
The potential of reconfigurable hardware for HPC cryptanalysis of SHA-1
No full textModern reconfigurable technologies can have a number of inherent advantages for cryptanalytic applications. Aimed at the cryptanalysis of the SHA-1 hash function, this work explores this potential showing new approaches inherently based on hardware reconfigurability, enabling algorithm and architecture exploration, input-dependent system specialization, and low-level optimizations based on static/dynamic reconfiguration. As a result of this approach, we identified a number of new techniques, at both the algorithmic and architectural level, to effectively improve the attacks against SHA-1. We also defined the architecture of a high-performance FPGA-based cluster, that turns out to be the solution with the highest speed/cost ratio for SHA-1 collision search currently available. A small-scale prototype of the cluster enabled us to reach a real collision for a 72-round version of the hash function
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