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Switch level optimization for CMOS circuits
No full textDue to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to [email protected], referencing the URI of the item.Includes bibliographical references.Issued also on microfiche from Lange Micrographics.In this report, 'Input vs Path Matrix 'Techique' and 'Node vs Input Matrix Technique' techniques for reducing transistor count in the pull-up and the pull-down array of CMOS circuits are proposed. Also, algorithms for optimization of both the pull-up tree and the pull-down tree, based on the above techniques, which results in a reduced number of transistors in the optimized tree in comparison to the original structure of CMOS circuits are proposed. A comparison has been done for area, delay and power of the optimized and unoptimized CMOS structures. Simulations for power and delay have been done in HSPICE [8] for both the optimized and unoptimized CMOS structures. Some of the optimized CMOS structures are the multiplexers, adders and gray to binary converters. The optimized CMOS structures have been found to be faster, lower in power dissipation and taking less layout area in comparison to the unoptimized CMOS structures. The above techniques can also be applied to the Pseudo-NMOS and Dynamic CMOS circuits besides the regular CMOS circuits
