247 research outputs found
Selected Songs of Dinos Constantinides (B. 1929).
No full textDr. Dinos Constantinides, a prolific composer of Greek origin whose works are performed throughout the world, is Boyd Professor of Music and Coordinator of Composition Studies at the Louisiana State University School of Music. His music has received many awards, including first prize in the 1981 Brooklyn College International Chamber Opera Competition, the 1985 First Midwest Chamber Opera Conference, and the 1997 Delius Composition Contest. Dr. Dinos Constantinides writes Twentieth-Century contemporary music that is fresh, passionate, and deserves to be heard by a broader public. The purpose of this document is to better acquaint the reader with the composer, Dr. Dinos Constantinides and selected song compositions from the Four Songs on Poems of Sappho, Mutability, the Four Greek Songs, and Reflections VI-The Tyger. Other than modest citations in reference volumes and via the internet, little information is dedicated to his contributions as a composer of song. The author attempts to augment the aforementioned materials with new information that will provide a springboard for others interested in further study of the composer and his music. Chapter One is a brief biographical sketch of the composer\u27s early life, musical training, and development as a composer. Chapter Two examines the poets chosen by Dr. Constantinides for these songs. Chapter Three surveys nine selected vocal songs, which were performed on the author\u27s lecture/recital. The appendices include IPA transcriptions of The Four Greek Songs , and an annotated catalog of Dr. Dinos Constantinides\u27 songs. In all of his compositions for voice, Dr. Dinos Constantinides seeks to paint a musical landscape of the imagery inspired by the text. Through the use of Twentieth-Century compositional techniques, his Greek culture, and his unique sense of style, he has contributed songs which are lyric and communicative, and are of lasting value to the solo song repertoire
Clinicopathological factors and survival outcomes of signet-ring cell and mucinous carcinoma versus adenocarcinoma of the colon and rectum: a systematic review and meta-analysis
No full textBackground:
Histological subtypes of colorectal cancer may be associated with varied prognostic features. This systematic review and meta-analysis aimed to compare clinicopathological characteristics, recurrence and overall survival between colorectal signet-ring cell (SC) and mucinous carcinoma (MC) to conventional adenocarcinoma (AC).
Methods:
A literature search of MEDLINE, EMBASE, Ovid and Cochrane Library was performed for studies that reported data on clinicopathological and survival outcomes on SC and/or MC versus AC from January 1985 to May 2020. Meta-analysis was performed using random-effect models and between-study heterogeneity was assessed.
Results:
Thirty studies of 1,087,055 patients were included: 11,510 (1.06%) with SC, 110,179 (10.13%) with MC and 965,366 (88.81%) with AC. Patients with SC were younger than patients with AC (WMD − 0.47; 95% CI − 0.84 to –0.10; I2 88.6%; p = 0.014) and more likely to have right-sided disease (OR 2.12; 95% CI 1.72–2.60; I2 82.9%; p < 0.001). Locoregional recurrence at 5 years was more frequent in patients with SC (OR 2.81; 95% CI 1.40–5.65; I2 0.0%; p = 0.004) and MC (OR 1.92; 95% CI 1.18–3.15; I2 74.0%; p = 0.009). 5-year overall survival was significantly reduced when comparing SC and MC to AC (HR 2.54; 95% CI 1.98–3.27; I2 99.1%; p < 0.001 and HR 1.38; 95% CI 1.19–1.61; I2 98.6%; p < 0.001, respectively).
Conclusion:
SC and MC are associated with right-sided lesions, advanced stage at presentation, higher rates of recurrence and poorer overall survival. This has strong implications towards surgical and oncological management and surveillance of colorectal cancer
Concerto for Cello and Orchestra and a Comparative Study of the Pedagogical Methods of Nadia Boulanger and Dr. Dinos Constantinides
No full textThe first part of this dissertation is an original music composition for orchestra entitled, Concerto for Cello and Orchestra. In studying the life of pianist and conductor Daniel Barenboim (November 15, 1942-), I discovered a recording of his beautiful and gifted wife Jacqueline Mary Du Pré, (January 26, 1945 – October 19, 1987) performing Edward Elgar\u27s Cello Concerto in E minor, Op. 85. This experience was the beginning of a love triangle between Elgar, Barenboim, and Du Pré. An attraction to Jacqueline goes deeper than just the music and the cello. Her career was not long due to multiple sclerosis which forced her to stop performing at the age of twenty-eight. Barbara (my wife) was afflicted with this crippling disease, and our relationship began with both of us being musicians (Trumpet and French horn). The second part of the dissertation is a comparative study of the pedagogical methods of Nadia Boulanger and Dr. Dinos Constantinides. Chapter 1 serves as an introduction of Nadia Boulanger and Dinos Constantinides in a biographical sketch. Chapter 2 uncovers the teaching of Nadia Boulanger and her connection to young successful American composers. Chapter 3 is an eyewitness account of the teaching of Dr. Dinos Constantinides by the author of this document. Chapter 4 shows a comparison of similarities and differences between the teaching of Nadia Boulanger and Dr. Dinos Constantinides. Chapter 5 is a summary and conclusion of the pedagogical methods of Nadia Boulanger and Dr. Dinos Constantinides
Design Exploration of an FPGA-Based Multivariate Gaussian Random Number Generator
No full textMonte Carlo simulation is one of the most widely used techniques for computationally
intensive simulations in a variety of applications including mathematical
analysis and modeling and statistical physics. A multivariate Gaussian
random number generator (MVGRNG) is one of the main building blocks of
such a system. Field Programmable Gate Arrays (FPGAs) are gaining increased
popularity as an alternative means to the traditional general purpose
processors targeting the acceleration of the computationally expensive random
number generator block due to their fine grain parallelism and reconfigurability
properties and lower power consumption.
As well as the ability to achieve hardware designs with high throughput it
is also desirable to produce designs with the flexibility to control the resource
usage in order to meet given resource constraints. This work proposes a novel
approach for mapping a MVGRNG onto an FPGA by optimizing the computational
path in terms of hardware resource usage subject to an acceptable
error in the approximation of the distribution of interest. An analysis on the
impact of the error due to truncation/rounding operation along the computational path is performed and an analytical expression of the error inserted into
the system is presented.
Extra dimensionality is added to the feature of the proposed algorithm by
introducing a novel methodology to map many multivariate Gaussian random
number generators onto a single FPGA. The effective resource sharing techniques
introduced in this thesis allows further reduction in hardware resource
usage.
The use of MVGNRG can be found in a wide range of application, especially
in financial applications which involve many correlated assets. In this
work it is demonstrated that the choice of the objective function employed
for the hardware optimization of the MVRNG core has a considerable impact
on the final performance of the application of interest. Two of the most important
financial applications, Value-at-Risk estimation and option pricing are
considered in this work
ATHEENA: Automated Toolflow for Hardware Early-Exit Network Acceleration
No full textThe continued need for improvements in accuracy, throughput, and efficiency of Deep Neural Networks has resulted in a multitude of static parameter reduction methods, like quantisation and pruning, which leverage the custom architectures possible on FPGAs. However, the potential of these solutions is already well exploited, reaching the limits of what can be achieved by reducing the number or size of the parameters while still maintaining accuracy. We propose a shift of focus to input-dependent computation to improve efficiency and reduce the average compute required for inference. Early-Exit (EE) networks have become an increasingly popular way to implement dynamic parameter reduction by varying network depth, essentially customising the computation level according to the difficulty of an input at run-time.
We create Automated Toolflow for Hardware Early-Exit Network Acceleration (ATHEENA), an automated, open-source CNN-to-FPGA toolflow which utilises the probability of samples exiting early from EE networks to optimally allocate the limited resources of an FPGA to different sections of the network. This ultimately results in improved throughput. The toolflow uses the data-flow model of the existing fpgaConvNet tool, extended to support Early-Exit networks, as well as Design Space Exploration (DSE) to optimise the generated streaming architecture hardware with the goal of increasing throughput/reducing area while maintaining accuracy. To this end, we incorporate abstracted hardware models, based on Queueing Theory, to aid the DSE with a more accurate analysis of performance and resource requirements. This improves the robustness of the accelerator.
Experimental results on three different networks demonstrate a throughput increase of 2.00 to 3.12 times compared to an optimised baseline network implementation with no early exits. Additionally, the toolflow can achieve a throughput matching the same baseline with as low as 48% of the resources the baseline requires
Forecasting Financial Time Series using Linear Predictive Filters
No full textForecasting financial time series is regarded as one of the most challenging applications
of time series prediction due to their dynamic nature. However, it is the fundamental
element of most investment activities thus attracting the attention of practitioners and
researchers for many decades.
The purpose of this research is to investigate and develop novel methods for the prediction
of financial time series considering their dynamic nature. The predictive performance
of asset prices time series themselves is exploited by applying digital signal
processing methods to their historical observations. The novelty of the research lies in
the design of predictive filters by maximising their spectrum flatness of forecast errors.
The filters are then applied to forecast linear combinations of daily open, high, low
and close prices of financial time series.
Given the assumption that there are no structural breaks or switching regimes in a
time series, the sufficient and necessary conditions that a time series can be predicted
with zero errors by linear filters are examined. It is concluded that a band-limited
time series can be predicted with zero errors by a predictive filter that has a constant
magnitude response and constant group delay over the bandwidth of the time series.
Because real world time series are not band-limited thus cannot be forecasted without
errors, statistical tests of spectrum flatness which evaluate the departure of the spectral
density from a constant value are introduced as measures of the predictability of
time series. Properties of a time series are then investigated in the frequency domain using its spectrum flatness. A predictive filter is designed by maximising the error
spectrum flatness that is equivalent to maximise the “whiteness” of forecast errors in
the frequency domain.
The focus is then placed on forecasting real world financial time series. By applying
spectrum flatness tests, it is found that the property of the spectrum of a linear
combination of daily open, high, low and close prices, which is called target prices, is
different from that of a random walk process as there are much more low frequency
components than high frequency ones in its spectrum. Therefore, an objective function
is proposed to derive the target price time series from the historical observations of
daily open, high, low and close prices. A predictive filter is then applied to obtain
the one-step ahead forecast of the target prices, while profitable trading strategies
are designed based on the forecast of target prices series. As a result, more than
70% success ratio could be achieved in terms of one-step ahead out-of-sample forecast
of direction changes of the target price time series by taking the S&P500 index for
example
Learning boolean circuits from examples
No full textThe design of efficient computer systems depends heavily on the ability to reduce the complexity of the underlying hardware. This is particularly important in the context of approximate computing, where Boolean circuits can be designed to produce approximate results with reduced hardware complexity, leading to smaller circuits with improved performance. One approach to achieving this is through the use of learning algorithms to automatically synthesize Boolean circuits from input-output examples. By integrating concepts from information theory and measure theory, it is possible to develop algorithms for learning Boolean circuits that are not only more accurate but also more efficient. This significance is amplified when immersed in the process of learning from examples, wherein the primary objective is to discern patterns and relationships within the data, laying the foundation for informed predictions or decisions. The work presented in this thesis aims to explore the application of mathematical quantifiers of information and uncertainty in datasets to improve the learning of corresponding Boolean circuits. In the first approach, mutual information is used to iteratively identify single output Boolean variables that optimize output information and reduce circuit area. The second approach focuses on simplifying Boolean circuits by removing logical gates using mutual information. This results in a significant reduction of 31% in area and 30% in delay for a 4% error rate, leading to more efficient circuits. In the third approach, the Wasserstein measure is used to learn Boolean circuits that leverage word-level information. These circuits can compete with machine learning techniques for MNIST classification while using 70 times less area. Moreover, for image processing filters, the learned Boolean circuit is 52% smaller than the exact model, while maintaining good accuracy.Open Acces
Zinc alpha-2-glycoprotein as a potential novel urine biomarker for the early diagnosis of prostate cancer
No full textA digital polar transmitter for multi-band OFDM Ultra-WideBand
No full textLinear power amplifiers used to implement the Ultra-Wideband standard must be
backed off from optimum power efficiency to meet the standard specifications and
the power efficiency suffers. The problem of low efficiency can be mitigated by polar
modulation. Digital polar architectures have been employed on numerous wireless
standards like GSM, EDGE, and WLAN, where the fractional bandwidths achieved
are only about 1%, and the power levels achieved are often in the vicinity of 20 dBm.
Can the architecture be employed on wireless standards with low-power and high
fractional bandwidth requirements and yet achieve good power efficiency?
To answer these question, this thesis studies the application of a digital polar transmitter
architecture with parallel amplifier stages for UWB. The concept of the digital
transmitter is motivated and inspired by three factors. First, unrelenting advances
in the CMOS technology in deep-submicron process and the prevalence of low-cost
Digital Signal processing have resulted in the realization of higher level of integration
using digitally intensive approaches. Furthermore, the architecture is an evolution
of polar modulation, which is known for high power efficiency in other wireless applications.
Finally, the architecture is operated as a digital-to-analog converter which
circumvents the use of converters in conventional transmitters.
Modeling and simulation of the system architecture is performed on the Agilent Advanced
Design System Ptolemy simulation platform. First, by studying the envelope
signal, we found that envelope clipping results in a reduction in the peak-to-average
power ratio which in turn improves the error vector magnitude performance (figure
of merit for the study). In addition, we have demonstrated that a resolution of three
bits suffices for the digital polar transmitter when envelope clipping is performed.
Next, this thesis covers a theoretical derivation for the estimate of the error vector
magnitude based on the resolution, quantization and phase noise errors. An analysis
on the process variations - which result in gain and delay mismatches - for a
digital transmitter architecture with four bits ensues. The above studies allow RF
designers to estimate the number of bits required and the amount of distortion that
can be tolerated in the system.
Next, a study on the circuit implementation was conducted. A DPA that comprises
7 parallel RF amplifiers driven by a constant RF phase-modulated signal and 7
cascode transistors (individually connected in series with the bottom amplifiers)
digitally controlled by a 3-bit digitized envelope signal to reconstruct the UWB
signal at the output. Through the use of NFET models from the IBM 130-nm
technology, our simulation reveals that our DPA is able to achieve an EVM of -
22 dB. The DPA simulations have been performed at 3.432 GHz centre frequency
with a channel bandwidth of 528 MHz, which translates to a fractional bandwidth
of 15.4%. Drain efficiencies of 13.2/19.5/21.0% have been obtained while delivering
-1.9/2.5/5.5 dBm of output power and consuming 5/9/17 mW of power.
In addition, we performed a yield analysis on the digital polar amplifier, based
on unit-weighted and binary-weighted architecture, when gain variations are introduced
in all the individual stages. The dynamic element matching method is also
introduced for the unit-weighted digital polar transmitter. Monte Carlo simulations
reveal that when the gain of the amplifiers are allowed to vary at a mean of 1 with a
standard deviation of 0.2, the binary-weighted architecture obtained a yield of 79%,
while the yields of the unit-weighted architectures are in the neighbourhood of 95%.
Moreover, the dynamic element matching technique demonstrates an improvement
in the yield by approximately 3%.
Finally, a hardware implementation for this architecture based on software-defined
arbitrary waveform generators is studied. In this section, we demonstrate that the error vector magnitude results obtained with a four-stage binary-weighted digital polar
transmitter under ideal combining conditions fulfill the European Computer Manufacturers
Association requirements. The proposed experimental setup, believed to
be the first ever attempted, confirm the feasibility of a digital polar transmitter architecture
for Ultra-Wideband. In addition, we propose a number of power combining
techniques suitable for the hardware implementation. Spatial power combining, in
particular, shows a high potential for the digital polar transmitter architecture.
The above studies demonstrate the feasibility of the digital polar architecture with
good power efficiency for a wideband wireless standard with low-power and high
fractional bandwidth requirements
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