67 research outputs found
A Framework for Integration of Knowledge Management and Business Process Management
No full textRecently, several attempts have been made to introduce the process concept to knowledge management (KM) or the knowledge concept to business process management (BPM) in order to combine the advantages of the two approaches. However, clear description about their interrelationship or a comprehensive framework to combine them has not been provided. This paper explores how KM and BPM can complement each other and proposes a framework to integrate the two paradigms. The concept of process knowledge proposed by this paper focuses on the importance of business processes as knowledge, which is overlooked by existing KM or BPM research efforts. The paper proposes a framework that combines and extends the functionalities of existing knowledge management systems (KMSs) and business process management systems (BPMSs) by identifying the functionalities required to manage process knowledge from the lifecycle perspective of both knowledge management and business process management. A prototype system is also presented to demonstrate the
feasibility of the proposed framework.clos
AN XML-BASED PROCESS REPOSITORY AND PROCESS QUERY LANGUAGE FOR INTEGRATED PROCESS MANAGEMENT
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A BUSINESS PROCESS SIMULATION FRAMEWORK INCORPORATING THE EFFECTS OF ORGANIZATIONAL STRUCTURE
No full textOrganizations constantly change their business processes and/or organizational structure to innovate and adapt to the rapidly changing environment. Business process simulation is one of the most popular methodologies for more effectively predicting the effects of process and organizational redesign. Most existing approaches, however, consider only business processes and not organizational structures that can significantly affect business process performance. This study presents a framework for incorporating the effects of organizational structure into business process simulation. Further, it demonstrates how to use and analyze the proposed model. Finally, a case study of the Korean prosecutor's office is presented to illustrate the importance and feasibility of the proposed approach, which will enable a more precise prediction of the changes caused by process and organizational redesignopen
A 333TOPS/W Logic-Compatible Multi-Level Embedded Flash Compute-In-Memory Macro with Dual-Slope Computation
No full textComputing-in-memory (CIM) has been an ongoing prominent research area for easing the energy efficiency of machine learning tasks in edge devices. Recently, embedded non-volatile memory (eNVM) CIM architectures have been popular as an edge device, where it can turn off their supply during standby for low power consumption. However, most eNVMs (e.g., MRAMs and RRAMs) require the use of specialized technologies and are mostly used as single-level cell (SLC) data storage [2], [3]. In the technologies that do not provide eNVMs, logic-compatible single-poly non-volatile embedded flash (eflash) memory [1] can be considered an alternative. Although the cell area of the single-poly non-volatile eflash is significant, we can considerably compensate for the cell area penalty by using multi-level cells (MLCS). Further, in eNVM CIMs, the analog computations must be quantized with an ADC, where the SAR ADCs are a popular conversion topology. However, SAR ADC designs result in significant power consumption and area overhead due to its capacitor DAC driving and high accuracy comparators [5]. In this work, we propose to overcome such challenges by proposing 1) a logic-compatible single-poly nonvolatile eflash memory macro using MLC and an SLC at the same time to increase computation density while maintaining a reasonable signal margin, 2) a resolution configurable differential SAR TDC used for both memory programming and computing with replacing analog voltage comparators to inverters in order to reduce power consumption and area, and 3) an energy-efficient 2's complement dual-slope computation with MLC and SLC sharing a single differential TDC for multi-bit weight computation. We fabricated the proposed eFlash CIM macro in a 65 ~nm CMOS process. Our measurements show that the proposed CIM macro achieves up to 333 TOPSM energy efficiency and 186.2 GOPS throughput
A 0.9V 2MHz 6.4x-Slope-Boosted Quadrature-Phase Relaxation Oscillator with 164.2dBc/Hz FoM and 62.5ppm Period Jitter in 0.18μm CMOS
No full textAs a low-cost, small-sized alternative to crystal oscillators, RC oscillators have emerged and are used for on-chip reference clocks [1-3] and time-based sensor nodes [4]. Since these types of oscillators operate with the time period defined by an RC time constant, it is inherently advantageous in frequency stability, energy efficiency, and period jitter. These oscillators utilize a predefined reference voltage level to convert the RC charging/discharging voltage waveform into its output time-domain clock. in this process, any added delay causes frequency instability, and circuit voltage noises are converted into the period jitter. DLL-based [1] and FLLbased [2-3] structures suppress this delay using their loop dynamics, but their low-power timing-detection circuits lead to increase voltage noise. The swing-boosted technique [3-5] can improve this period jitter performance by reducing the voltage-noise-to-jitter conversion ratio. However, the maximum swing of these structures is limited by supply rail and high-voltage stress to transistor gates. To overcome these limits, this paper presents a quadrature-phase swing-boosted RC oscillator consisting of multiple inter-operating RC oscillator cells. The proposed quadrature RC oscillator achieves an excellent period jitter performance of 62. 5ppm and the best-ever-reported FoM of 164. 2dBc/Hz, which is 2dB higher than the state-of-the-art. This concept can be extended to an N-phase swing-boosting technique to manipulate the RC charging/discharging waveform by adjusting N. © 2023 IEEE
A SiPM Readout IC Embedded in a Boost Converter for Mobile Dosimeters
No full textA power-and hardware-efficient radiation detection system is presented for mobile dosimeter. Thanks to the duty quantizer embedded in boost converter for driving radiation detector, the radiation signal can be converted to digital value without implementing seabsparate sensor interface circuits. The prototype IC is implemented using 0.18-μm BCD process, and achieves 0.217μArms of integrated input referred noise enough low to measure radiation signal without using complex readout IC
31.2 A 0.9V 28MHz Dual-RC Frequency Reference with 5pJ/Cycle and ±200 ppm Inaccuracy from -40°C to 85°C
No full textWireless sensor nodes in battery-powered internet-of-things (loT) applications require a stable on-chip frequency reference with low energy (<10 pJ / cycle) and high frequency stability (below ±300ppm). CMOS RC frequency references are promising due to their low-cost integration and high energy efficiency [1] –[5]. Conventional RC references, however, achieve only moderate accuracy (a few %) due to the large temperature coefficient (TC) of on-chip resistors [3]. First-order TC compensation can be achieved by combining resistors with complementary TCs [1], [2]. Although this is energy efficient (<6 pJ / cycle), it only partially compensates for the resistors’ high-order TCs, limiting the resulting accuracy to about ±500 ppm. Better accuracy (±100 ppm [4]) can be achieved by using the output of a digital temperature sensor (TS) to perform a polynomial correction of the phase-shift (μp,T) of an RC filter (Fig. 31.2.1). Alternatively, the phase-shifts (μp. and μN) of two RC filters with complementary TCs can be linearized (Tp. and T N ) and combined in the digital domain. Such dual-RC frequency references can also achieve good accuracy (±200 ppm [5]). However, both architectures employ an analog phase-domain ΔΣ modulator (Φ−ΔΣM) for each RC filter, which consumes significant energy (25pJ/cycle [4] and 107pJ/ cycle [5]) and area (0.3mm2[4]. and 1.65mm2[5]).Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.MicroelectronicsElectronic Instrumentatio
An 8MHz 31.25kS/s Impedance-Monitoring IC Based on IF-Sampling Architecture with a Band-Pass Delta-Sigma ADC
No full textWe present an impedance-monitoring IC achieving a wide frequency range (FR) and fast output data rate (ODR). The proposed IC support a wide FR with improved spectral density by down-converting the signal to the intermediate frequency (fIF) in front of the instrumentation amplifier (IA) using the LO signal generated by a single-side-band (SSB) mixer. The proposed IF-sampling architecture does not require narrow-bandwidth (BW) low-pass filter (LPF), resulting in a fast ODR. A time-interleaved (TI) DFT is also employed to further improve the ODR. A band-pass delta-sigma ADC (BP-ΔΣ-ADC) with the auto-calibration and BP truncation is adopted to achieve the best noise performance at fIF. The fabricated IC achieves 0.35ΩRMS resolution in the FR from 4kHz to 8MHz with 122.1Hz BW while providing the ODR up to 31.25kS/s
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