1,720,980 research outputs found
Electrical Performance Analysis of Glass Interposer Channel and Power Distribution Network
No full textIn this paper, we emphasize superiority of glass interposers and address challenges with proper solutions. Electrical performance of the glass interposer channels is superior to other interposers such as silicon and organic. However, glass interposers are vulnerable to noises generated in power distribution network (PDN). We propose decoupling solutions for glass interposers to solve the PDN noise issues
Power Distribution Network (PDN) Design and Analysis of A Single and. Double-Sided High Bandwidth Memory (HBM) Interposer for 2.5D Terabtye/s Bandwidth System
No full textEye-diagram Estimation and Analysis of High-Bandwidth Memory (HBM) Interposer Channel with Crosstalk Reduction Schemes on 2.5D and 3D IC
No full textSignal Integrity of Bump-less High-speed Through Silicon Via Channel for Terabyte/s Bandwidth 2.5D IC
No full textDesign and Analysis of Power Distribution Network (PDN) for High Bandwidth Memory (HBM) Interposer in 2.5D Terabyte/s Bandwidth Graphics Module
No full textElectrical Performance Analysis of Low-Cost and Ultra-Thin Glass Interposer: Advantages, Challenges and Solutions
No full textSignal and Power Integrity (SI/PI) Analysis of Heterogeneous Integration Using Embedded Multi-die Interconnect Bridge (EMIB) Technology for High Bandwidth Memory (HBM)
No full textChannel Characteristic-Based Deep Neural Network Models for Accurate Eye Diagram Estimation in High Bandwidth Memory (HBM) Silicon Interposer
No full textIn this article, for the first time, we propose channel characteristic-based deep neural network (DNN) models for accurate eye-height (EH) and eye-width (EW) estimation of high bandwidth memory (HBM) silicon interposer channels. The proposed models preprocess the design parameters that are highly relevant to the characteristics of the HBM channels. By taking account of the contribution of each design parameter to the eye diagram, the proposed models can accurately estimate the EH and EW of the channels even with a limited number of datasets. For verification, the proposed DNN models were applied to the microstrip and stripline channels of an HBM silicon interposer. Only redistributed layer (RDL) was used to clearly see the effect of reflecting the channel characteristics of the proposed method. We compared the proposed DNN models with various regression methods and a conventional fully connected multilayer DNN model. As a result, the proposed DNN models reduced the EH and EW error rates by 22.7 and 43.9% compared to the other regression methods. In addition, the proposed DNN models not only reduced the error rates by 22.0-28.4% but also reduced the computing cost by 8.0-9.4%, compared to the conventional DNN model. Moreover, we compared the proposed models with various DNN models having other preprocessing structures. By showing 26.7 and 28.8% lower EH and EW error rates than the other DNN models, we validated that the proposed models properly consider the most dominant design factors in preprocessing.
Modeling and Signal Integrity Analysis of 3D XPoint Memory Cells and Interconnections with Memory Size Variations During Read Operation
No full text3D XPoint memory is one of the new memory using phase change memory (PCM) and ovonic threshold switch (OTS) with 20 nm 3-dimensional cross array structure. This memory is non-volatile and has better performance in terms of memory process speed than NAND flash memory and memory density than DRAM. The space between interconnections are close so, the voltage coupling affects to the adjacent interconnections during read operation. In this paper, we analyzed the 3D XPoint memory with memory size variation during read operation considering signal integrity (SI). For the analysis, we assumed the overall structure of the 3D XPoint memory and modeled the memory cell that consist of PCM and OTS as behavior model and the interconnections as RC model with 3D electromagnetic (EM) simulator. We fully simulated the 3D XPoint memory including memory behavior model, RC model of interconnections and peripheral circuits such as the addressor and current sense amplifier. With variation of the memory size during read operation, there are SI issues such as voltage coupling and drop trends through the interconnections
Reinforcement Learning-Based Optimal on-Board Decoupling Capacitor Design Method
No full textIn this paper, for the first time, we propose a reinforcement learning-based optimal on-board decoupling capacitor (decap) design method. The proposed method can provide optimal decap designs for a given on-board power distribution network (PDN). An optimal decap design refers to the optimized combination of decaps at proper positions to satisfy a required target impedance. Moreover, a minimum number of decaps should be assigned for optimal decap designs. The proposed method is applied to the test on-board PDN and successfully provided 37 optimal decap designs with 4 decaps assigned each. Self impedance of PDN with the provided design satisfied the required target impedance while minimizing the number of assigned decaps
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