715 research outputs found
Neuromorphic Engineering: From Neural Systems to Brain-Like Engineered Systems
Full text linkMorabito FC, Andreou AG, Chicca E. Neuromorphic Engineering: From Neural Systems to Brain-Like Engineered Systems. Neural Networks. 2013;45:1-3
A VLSI recurrent network of integrate-and-fire neurons connected by plastic synapses with long-term memory
Full text linkChicca E, Badoni D, Dante V, et al. A VLSI recurrent network of integrate-and-fire neurons connected by plastic synapses with long-term memory. IEEE Transactions on Neural Networks. 2003;14(5):1297-1307.Electronic neuromorphic devices with on-chip, on-line learning should be able to modify quickly the synaptic couplings' to acquire information about new patterns to be stored (synaptic plasticity) and, at the same time, preserve this information on very long time scales (synaptic stability). Here, we illustrate the electronic implementation of a simple solution to this stability-plasticity problem, recently proposed and studied in various contexts. It is based on the observation that reducing the analog depth of the synapses to the extreme (bistable synapses) does not necessarily disrupt the performance of the device as an associative memory, provided that 1) the number of neurons is large enough; 2) the transitions between stable synaptic states are stochastic; and 3) learning is slow. The drastic reduction of the analog depth of the synaptic variable also makes this solution appealing from the point of view of electronic implementation and offers a simple methodological alternative to the technological solution based on floating gates. We describe the full custom analog very large-scale integration (VLSI) realization of a small network of integrate-and-fire neurons connected by bistable deterministic plastic synapses which can implement the idea of stochastic learning. In the absence of stimuli, the memory is preserved indefinitely. During the stimulation the synapse undergoes quick temporary changes through the activities of the pre- and postsynaptic neurons; those changes stochastically result in a long-term modification of the synaptic efficacy. The intentionally disordered pattern of connectivity allows the system to generate a randomness suited to drive the stochastic selection mechanism. We check by a suitable stimulation protocol that the stochastic synaptic plasticity produces the expected pattern of potentiation and depression in, the electronic network. The proposed implementation requires only 69 x 83 mum(2) for the neuron and 68 x 47 mum(2) for the synapse (using a 0.6 mum, three metals, CMOS technology) and, hence, it is particularly suitable for the integration, of a large number of plastic synapses on a single chip
Stochastic synaptic plasticity in deterministic aVLSI networks of spiking neurons
Full text linkChicca E, Fusi S. Stochastic synaptic plasticity in deterministic aVLSI networks of spiking neurons. In: Rattay F, ed. Proceedings of the World Congress on Neuroinformatics. Vienna: ARGESIM/ASIM Verlag; 2001: 468-477.Stochastic learning solves the stability-plasticity problem (Fusi et al., 2000a)
but raises new issues related to the generation of the proper noise driving
the synaptic dynamics. Here we show that a simple, fully deterministic,
spike-driven synaptic device can make use of the network generated vari-
ability in the neuronal activity to drive the required stochastic mechanism.
Randomness emerges naturally from the interaction of deterministic neu-
rons, and no extra source of noise is needed. Learning and forgetting
rates of the network can be easily controlled by changing the statistics of
the spike trains without changing any inherent parameter of the synaptic
dynamics
A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity
Full text linkIndiveri G, Chicca E, Douglas RJ. A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity. IEEE Transactions on Neural Networks. 2006;17(1):211-221.We present a mixed-mode analog/digital VLSI device comprising an array of leaky integrate-and-fire (I&F) neurons, adaptive synapses with spike-timing dependent plasticity, and an asynchronous event based communication infrastructure that allows the user to (re)con figure networks of spiking neurons with arbitrary topologies. The asynchronous communication protocol used by the silicon neurons to transmit spikes (events) off-chip and the silicon synapses to receive spikes from the outside is based on the "address-event representation" (AER). We describe the analog circuits designed to implement the silicon neurons and synapses and present experimental data showing the neuron's response properties and the synapses characteristics, in response to AER input spike trains. Our results indicate that these circuits can be used in massively parallel VLSI networks of I&F neurons to simulate real-time complex spike-based learning algorithms
A Neuromorphic VLSI System for Modeling Spike-Based Cooperative Competitive Neural Networks
No full textChicca E. A Neuromorphic VLSI System for Modeling Spike-Based Cooperative Competitive Neural Networks. Zürich, Switzerland: ETH Zürich; 2006
Characterizing the firing properties of an adaptive analog VLSI neuron
Full text linkBen Dayan Rubin D, Chicca E, Indiveri G. Characterizing the firing properties of an adaptive analog VLSI neuron. Biologically Inspired Approaches to Advanced Information Technology. 2004;3141:189-200.We describe the response properties of a compact, low power, analog circuit that implements a model of a leaky-Integrate & Fire (I&F) neuron, with spike-frequency adaptation, refractory period and voltage threshold modulation properties. We investigate the statistics of the circuit's output response by modulating its operating parameters, like refractory period and adaptation level and by changing the statistics of the input current. The results show a clear match with theoretical prediction and neurophysiological data in a given range of the parameter space. This analysis defines the chip's parameter working range and predicts its behavior in case of integration into large massively parallel very-large-scale-integration (VLSI) networks
A VLSI neuromorphic device with 128 neurons and 3000 synapses: area optimization and design
No full textChicca E. A VLSI neuromorphic device with 128 neurons and 3000 synapses: area optimization and design.; 1999
Firing proprieties of an adaptive analog VLSI neuron
Full text linkBen Dayan Rubin D, Chicca E, Indiveri G. Firing proprieties of an adaptive analog VLSI neuron. Presented at the Proceedings of Bio-ADIT, Lausanne, Switzerland.We describe the response properties of a compact, low power, analog circuit that implements a model of a leaky I&F neuron, with spike-frequency adaptation, refractory period and voltage threshold modulation properties. We investigate the statistics of the circuit's output response by modulation its operating parameters, like refractory period and adaptation level and by changing the statistics of the input current. The results show a clear match with theoretical and neurophysiological data in a given range of the parameter space. This analysis defines the chip's parameter working range and predicts its behavior in case of integration into large massively parallel VLSI networks
A VLSI neuromorphic device for implementing spike-based neural networks
Full text linkIndiveri G, Chicca E. A VLSI neuromorphic device for implementing spike-based neural networks. Presented at the Proceedings of the 21st Italian Workshop on Neural Nets (WIRN).We present a neuromorphic VLSI device which comprises hybrid analog/digital circuits for implementing networks of spiking neurons. Each neuron integrates input currents from a row of multiple analog synaptic circuit. The synapses integrate incoming spikes, and produce output currents which have temporal dynamics analogous to those of biological post synaptic currents. The VLSI device can be used to implement real-time models of cortical networks, as well as real-time learning and classification tasks. We describe the chip architecture and the analog circuits used to implement the neurons and synapses. We describe the functionality of these circuits and present experimental results demonstrating the network level functionality
Floating-Gate-Based Intrinsic Plasticity with Low-Voltage Rate Control
No full textNease S, Chicca E. Floating-Gate-Based Intrinsic Plasticity with Low-Voltage Rate Control. In: 2016 IEEE International Symposium on Circuits and Systems (ISCAS). Piscataway, NJ: IEEE; 2016
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