1,720,978 research outputs found
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique
No full textThis paper analyzes and compares two popular methods to widen the modulation bandwidth of a phase-locked loop, i.e., the pre-emphasis and the two-point injection technique. The analysis reveals that both architectures have the same sensitivity to gain errors and nonlinearity in the loop, though, compared with the pre-emphasis, the two-point injection scheme features less sources of error and does not require a phase detector with wide range and tight linearity requirements. The verification of the analysis as well as the comparison of the two modulation techniques is carried out on an accurate time-domain model of a 60-GHz digital phase-locked loop, taken as a case study and used to generate wideband chirp signals for a radar system
Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars
No full textThe need for low-noise, highly-linear, programmable chirp generators makes digital phase-locked loops (DPLLs) an attractive solution for radar sensors. This paper presents a general analysis and comparison of the two main techniques enabling wideband frequency modulation (FM) in PLLs, namely the two-point injection and the pre-emphasis. It is shown that while the two topologies are equivalent in term of mismatch error suppression, the required input range for the time-to-digital converter (TDC) is substantially lower in the two-point injection scheme, thus relaxing the TDC power consumption and linearity
Wideband chirp generation techniques in digital phase-locked loops
No full textIn this paper in-depth analysis and comparison of two popular FM techniques, namely, two-point modulation and pre-emphasis of the modulation signal are presented. Both modulation enhancement techniques were implemented in the time domain model of an all-digital phase-locked loop (ADPLL). Their performance is evaluated based on Matlab simulations for different type of chirps. Obtained results show that chirps with the period of 0.1ms and peak-to-peak bandwidth of 1GHz can be generated with linearity better than 1% by employing either of these techniques. Additionally, advantages of two-point modulation with respect to ADPLL building block requirements are demonstrated
Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators
No full textThe direct frequency modulation of a phase locked loop suffers from limited modulation bandwidth. To overcome this limitation, the modulation signal can be pre-emphasized by means of a high-pass filter. Unfortunately, the incorrect equalization of the PLL transfer function causes modulation error. This paper introduces a new method to adaptively match the transfer functions of the PLL and the pre-emphasis filter over environmental and process variations. The technique is verified using a time-domain model of a digital PLL designed for the generation of chirp signals for FMCW radar sensors. The new adaptive digital pre-emphasis technique enables the generation of highly-linear fast chirps with significant reduction of the idle time
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range
No full textDigital phase-locked loops (DPLLs) based on binary phase detectors (BPDs) avoid power-hungry high-resolution time/digital converters (TDCs) while demonstrating advantages in area, power consumption, and design complexity. The introduction of digital/time converters (DTCs) enables fractional-N resolution at high spectral purity [1]. The design of a bang-bang digital PLL for wireless standards has two main challenges: quantization noise must be kept below the tolerable spot phase noise and fast lock must be guaranteed even for wide frequency steps. However, the overload of the BPD causes bang-bang PLLs to fail lock or to exhibit extremely long transients. A similar issue appears in the design of sub-sampling PLLs. This problem is exacerbated when the bang-bang PLL is designed for low phase noise for the tight resolution required of the digitally controlled oscillator (DCO). Fast locking techniques are usually based on the use of lookup tables [2], finite state machine [3], or gear shifting techniques, mostly in the field of clock-and-data recovery circuits (CDR) where spot noise performance is less of a concern. High-performance bang-bang PLLs (or subsampling PLLs) also include a frequency-aid circuit running in background [4], but its settling performance is seldom discussed
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise
No full textThis paper presents a novel technique to reduce the locking time in Digital Phase-Locked Loop (DPLL) based on Bang-Bang Phase Detector (BB-PD). The implemented 65-nm CMOS fractional-N frequency synthesizer generates an output signal between 3.7 and 4.1 GHz from a 52 MHz reference clock and improves the trade-off between phase noise, due to the loop quantization, and locking time, exploiting a digital locking loop that avoids look-up table (LUT) and finite state machine-based (FSM) locking schemes. Measurements show that the output signal spot noise at 20 MHz from the carrier is -150.7 dBc/Hz while the best locking time, for a coarse step of 364 MHz, is 115 μs, overcoming the locking time limitations and avoiding cycle slips that usually affect the 1-bit phase detector PLL
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS
No full textThis article describes the implementation of a 30-GHz frequency synthesizer. The target is to reduce the gap in terms of jitter-power product that exists between millimeter- wave and RF synthesizers, using a low-cost 65-nm LP CMOS technology. The circuit is a digitally intensive fractional-N phase-locked loop, which combines a sub-sampling bang-bang phase detector, a low-power divider-by-six prescaler with a novel injection scheme, and a digital technique reducing the output range of the digital-to-time-converter. The synthesizer can operate between 30.4 and 34.2 GHz with a frequency resolution of 191 Hz and with an integrated rms jitter below 180 and 197.6 fs for the integer-N and fractional-N channels, respectively. The sub-sampling loop can synthesize fast sawtooth chirps around 33.4 GHz with peak-to-peak amplitudes up to 1.14 GHz. The fractional spurs, measured at the 5-GHz prescaler output, are below −54 dBc, even considering near-integer channels. The power dissipation of 35 mW from the 1.2-V supply leads to a −238.6 dB of jitter-power figure of merit for fractional-N channels
A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL
No full textThis paper presents a 14GHz digital-intensive phase modulator circuit, which is able to enforce an arbitrary carrier phase change in one sample of a 200MHz clock. The architecture is based on a fractional-N bang-bang digital PLL exploiting an adaptive DCO-tuning requantizer, which mitigates the segmentation-induced nonlinearity of the DCO, and a novel deskewing circuit, which improves the EVM at high bit rates. The modulation error, expressed in terms of RMS value of the EVM, is below -42dB for a 250Mb/s 32-PSK modulated carrier. The phase modulator, integrated in a 28nm CMOS process, consumes 31.5mW power, achieving 0.13nJ/bit energy consumption
A 15.6-18.2 GHz digital bang-bang PLL with -63dBc in-band fractional spur
No full textThis paper describes a 15.6-18.2GHz fractional-N bang-bang digital PLL fabricated in 28nm CMOS. To compensate for the nonlinearity of the digital-to-time converter and reduce the level of fractional spurs, two alternative predistortion techniques are introduced. The adoption of those algorithms operating continuously in background is demonstrated to reduce the level of the in-band fractional spur at 300kHz from -20dBc to -57dBc and -63dBc, respectively. The fabricated PLL achieves FoM of -237.2dB
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation
Full text linkFrequency-modulated continuous-wave (FMCW) radars with high resolution require the generation of low-phase-noise, low-spurs, and highly linear chirp signals with large peak-to-peak value (chirp bandwidth) and a short period of the modulation signal [1]. In radar systems, the spot phase noise of the chirp generator is converted to the intermediate frequency of the receiver making it difficult to detect two close targets, while spurs cause the detection of false targets. For those reasons, medium-range radar applications in the 77-to-81GHz band typically specify spot phase noise lower than −90dBc/Hz at 1MHz offset and spur level below −50dBc. Unlike triangular chirps, saw-tooth chirps allow for a reduced dead time for range detection. However, any practical modulator needs a finite time (idle time) to make a large frequency jump at the end of the saw-tooth, and this limits the duty cycle of the saw-tooth. For instance, a fast saw-tooth chirp with 200kHz rate and 95% duty cycle leaves the idle time of only 250ns. Fractional-N PLLs can be used as chirp modulators. Unfortunately, low phase noise and spur levels require a narrow PLL bandwidth, while short idle time demands for a wide one. The two-point injection of the modulation signal, both from the modulus control of the divider and the tuning input of the voltage-controlled oscillator (VCO), is a known method to simultaneously achieve a narrow PLL bandwidth and fast modulation. However, even in that scheme, a frequency modulation error is mainly limited by gain mismatch between the two injection paths and by the linearity of the VCO [2]. In this work, a 20-to-24GHz digital bang-bang PLL, which uses the two-point modulation scheme to generate triangular and saw-tooth chirp signals, is presented. Unlike previous works [1-4], this architecture is able to generate fast saw-tooth chirps with the slope up to 173MHz/js, the idle time below 200ns, and the rms frequency error of better than 0.06%. The gain mismatch between the two modulation paths are automatically calibrated by a digital algorithm [5], and the input of the digitally controlled oscillator (DCO) is pre-distorted via an automatic background correction scheme, which compensates for the DCO nonlinearity
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