1,720,972 research outputs found
3. Tombeau du Cheikh 'Abdallah
No full textSimaïka Marcus H., Greg Robert Hyde, Sayyed Ahmad el-, Sayed Metoualli, Pauty Edmond. 3. Tombeau du Cheikh 'Abdallah. In: Comité de Conservation des Monuments de l'Art Arabe. Fascicule 36, exercice 1930-1932, 1936. p. 133
8° Coupole du cheikh Abdallah el-Dacrouri
No full textFranz Julius, Grand Pierre, Herz Max, Faouzi Abdel Hamid. 8° Coupole du cheikh Abdallah el-Dacrouri. In: Comité de Conservation des Monuments de l'Art Arabe. Fascicule 14, exercice 1897, 1898. p. 64
8° Tombeau du cheikh Abdallah Gafir el-Darb
No full textBarois Julien, Franz Julius, Bahgat Ali, Casanova Paul, Herz Max. 8° Tombeau du cheikh Abdallah Gafir el-Darb. In: Comité de Conservation des Monuments de l'Art Arabe. Fascicule 18, exercice 1901, 1901. p. 23
Energy-efficient digital electronic systems design for edge-computing applications, through innovative RISC-V compliant processors
Get PDFThe number of IoT devices has greatly increased over the years, so that they have invaded the electronic market. IoT describe a device-to-device communication without human interface. A large class of these devices are battery powered, and the energy consumption inside them is considered critical.
Today’s embedded IoT systems interface multiple peripherals such as sensors that perform continuous monitoring of the environment around it, and actuators that are controlled by the embedded systems. Also, they interface wireless devices for data transmissions. A part of their job includes some basic pre-processing of the data before transmitting it over those wireless networks. Such pre-processing “on the edge of the network” minimizes the data to be transmitted over the wireless channels, and only transmits the desired outputs.
In front of the increase demand to support pre-processing, such as computer vision and voice recognition, on small embedded systems on the edge of the network, they cannot completely satisfy those demands due to their little performance
In this study we demonstrate the performance and energy efficiency of interleaved multithreaded architectures, which can be used in an embedded system on the edge of the IoT interfacing multiple sensors and peripherals, each serviced by a different hardware thread. We show the optimal pipeline organization to use in such architectures, and we finally demonstrate how these architectures can be exploited to easily improve instruction level parallelism by integrating a convolutional neural networking accelerator that can perform very fast vector arithmetic operations, and finally benchmarking this accelerator by running a custom implementation of the VGG16 convolutional neural network.
The microprocessors presented are a part of a family of processing cores called Klessydra. The Klessydra microprocessors were written such that they have a pinout that are 100 percent identical with Riscy cores from PULPino SoC. The subset of the Klessydra cores presented in this thesis is called the Klessydra-T. The letter ‘T’ indicating that the cores are multithreaded, the Klessydra-T subset has two main implementations used throughout this thesis, they are Klessydra-T03 and Klessydra-T13. T03 and T13 for short.
The processor cores have been tested with the Modelsim / Questasim simulators. The cores have been synthesized on the 7-series FPGAs from Xilinx with the Vivado Synthesis tool. Synthesis and Post-synthesis simulations have been made. Dynamic Power estimations were calculated by Vivado from the power report generated by Modelsim after having simulated a post-synthesis Vivado netlist. FPGA synthesis was chosen as our target implementation, as they provide high reconfigurability, which allows the user to easily customize their own accelerator and make it adapt accordingly to their specific applications.
In our assessment throughout this thesis we nominated the T03 interleaved multithreaded processor as our optimal and most balanced pipeline organization. The T03 core had many advantages over other architectures, however it was only suitable to be used in control applications. T13 solves this problem by implementing superscalar hardware accelerators. A hybrid implementation of the hardware accelerator targeting thread level parallelism and slight data level parallelism was the approach yielding the highest performance and still maintaining a relatively low energy consumption for energy critical environments
Single event transient reliability analysis on a fault-tolerant RISC-V microprocessor design
No full textThe miniaturization of electronic devices and the improved operating speeds increase the likelihood of single event faults. Differently from Single Event Upset (SEU) faults, Single Event Transient (SET) faults generally affect combinational logic, making all voting systems vulnerable to errors. The proposed work uses an ad-hoc fault-simulation campaign employing signal glitching to identify SET vulnerabilities inside a RISC-V core already equipped with resilience logic against Single Event Upset (SEU) faults. The faults target the majority voting logic structures, highlighting how they can be susceptible to faults depending on the width of the injected pulses, and showing how the use of Buffered Triple Modular Redundancy (BTMR) allows decreasing the total failure probability due to erroneous majority voters. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2024
Mahmoud Zubeiri et la fondation du Parti de Dieu
No full textA la veille de l’an 2000, au cœur des équilibres politiques du Yémen, perdure une union que symbolise bien la personnalité du Cheikh Abdallah al-Ahmar. A la fois leader du Rassemblement Yéménite pour la Réforme (al-Tagamu‘ al-Yemeni lil-Islah, la puissante formation islamiste créée en 1990) et chef de la confédération Hâched, le plus important des rassemblements tribaux du nord, le "Cheikh Abdallah", souvent considéré comme la seconde personnalité politique du pays, est également président du..
Investigation on the optimal pipeline organization in RISC-V multi-threaded soft processor cores
No full textFPGA-synthesizable soft-processor cores are commonly used in many digital system applications with low medium production volume, to control heterogeneous dedicated computational units and I/O units. In such contexts, the inherently multi-tasking nature of the processor operation demands for a cost-effective and energy-efficient multi-threaded execution, either as multi-core architecture or multi-threaded single-core. This work presents an experimental exploration of microarchitecture design solutions for multi-threaded soft processor core implementations on FPGA. We report detailed quantitative results on resource utilization, performance and energy efficiency of the different solutions, varying the pipeline organizations, thread pool size, active thread count and voltage
A universal hardware emulator for verification IPs on FPGA: a novel and low-cost approach
No full textEfficient and cost-effective functional verification strategies are more and more essential in digital integrated system design. This paper presents a low-cost approach to meet this challenge, introducing a universal hardware emulator designed for verifying various Intellectual Property (IP) cores on FPGA. We demonstrate the practicality and performance of this emulator through a use-case of verifying an advanced Integer Arithmetic Logic Unit (ALU) for the RISC-V ISA vector extension.
The process of integration and the results obtained from the verification are presented and discussed. Preliminary findings indicate that the emulator can perform more than 1.1 million tests per second. This research contributes to the advancement of hardware verification techniques, providing researchers, universities, and small businesses with an accessible and effective solution
A RISC-V fault-tolerant soft-processor based on full/partial heterogeneous dual-core protection
Get PDFThe low probability of single event upsets (SEU) within particular satellite orbits, makes Commercial-off-the-shelf (COTS) electronic components a viable solution for space system implementation, thanks to the introduction of design-level fault tolerance techniques at the expense of some performance/energy/area penalty. This paper illustrates the design and validation of a novel RISC-V dual-core architecture, based on a computing paradigm that we refer to as full/partial heterogeneous multi-core protection. The approach relies on a small, low-performance, fully fault-tolerant core (LP core) coupled with a high-performance partially fault-tolerant core (HP core). The computing paradigm assumes the failure-exposed HP core executes computation intensive routines for relatively short periods of time, making the occurrence of failures a statistically unlikely situation, while the fully fault-tolerant LP core operates in critical control tasks and manages the failure recovery of the high-performance core. The execution time percentage in the LP core varies from a minimum of 11.4% up to a maximum of 91.3% while in the HP core it is between 8.7% and 88.6%, depending on the application. In the proposed study, both the cores belong to the RISC-V compliant Klessydra core family. The dual-core architecture also includes a watchdog timer controlled by the LP core and monitoring the non-protected HP core, and a context switch FIFO that speeds up the code and data switch between the two cores during failure recovery. A dedicated run-time software environment coordinates the execution of tasks on the high-performance core in a resilient fashion. The dual-core processor has been validated through extensive RTL simulations running in an UVM-based fault-injection environment, which emulates SEUs at various rates. Experimental results illustrate the benefits and limits obtained by using a heterogeneous architecture with different levels of protection and performance. The failure probability assuming a SEU fault occurrence can be reduced by a factor between 10X and 30X with respect to the non-protected architecture, leading to an average failure rate of up to 4.00E-06 per second with respect to 1.80E-05 per second in the non-protected architecture
Implementation of dynamic acceleration unit exchange on a RISC-V soft-processor
No full textUsing Artificial Intelligence (AI) techniques has become the best solution in many applications. By the end of Moore's Law, implementing a platform capable of such massive processing for edge-IoT applications has become a significant challenge. However, using static hardware accelerators can be an excellent solution; even so, they typically require a great deal of silicon area and are not optimized for all operation modes. Reconfigurable computing lets parts of the hardware change proportionally to the task during operation, allowing for optimized operation and the use of many hardware accelerators without requiring a large area. In this study, we present a dynamic acceleration unit exchange on a RISC-V soft-processor based on the open-source Klessydra-T13 RISC-V core. We show how reconfiguration can be used to make the hardware accelerator more flexible and improve its performance. As a case study, we show how reconfiguration techniques can be used to speed up AI architectures by reconfiguration of vector accelerator units
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