9 research outputs found
Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction
No full textToday's data-centric applications are incompatible with the predominant compute-centric computer architectures. The small on-chip memories of compute-centric computer architecture demand many energy-costly data transfers exposing the von-Neumann bottleneck. The Ferroelectric Field-Effect Transistor (FeFET) is an emerging Non-Volatile Memory technology enabling novel data-centric architectures that go far beyond von-Nuemann principles. FeFETs are very promising for a wide range of applications starting from on-chip memories to in-memory computing and even neuromorphic computing. Nevertheless, FeFET devices exhibit significant variations that can severely restrict their applicability. Temperature further exacerbates variation effects because it degrades ferroelectric parameters. Hence, it is indispensable to investigate and model design-time variations, run-time variations, and stochastic variations due to spatial fluctuation of ferroelectric domains under different temperatures. Dual-port FeFET has been recently proposed and demonstrated as novel structure that offers for the first time disturb-free read operation along with larger memory window (MW) compared to conventional FeFETs. However, all of the before-mentioned types of variations are amplified in such a new structure. In this work, the impact of temperature variation is analyzed for dual-port FeFETs for the first time in a cross-layer manner starting from the device level to the circuit/system levels and compared to conventional FeFET. We focus in our analysis on Hyperdimensional Computing (HDC), which is an emerging type of machine learning algorithm, that is being executed on top of FeFET-based in-memory circuits that perform efficient Hamming distance (i.e., similarity) computations. Through our cross-layer framework, we demonstrate the serious impact of variation on FeFET reliability despite the significant increase in the MW that dual-port FeFET offers. Even HDC is affected, despite its remarkable robustness against errors. All in all, our work reveals that a larger MW at the device level does not necessarily translate to benefits at the application level. Hence, investigating and modeling variability effects in a cross-layer manner is indispensable.</p
Nontraditional Design of Dynamic Logics Using FDSOI for Ultra-Efficient Computing
No full textIn this article, we propose a nontraditional design of dynamic logic circuits using fully-depleted silicon-on-insulator (FDSOI) FETs. FDSOI FET allows the threshold voltage ( ) to be adjustable (i.e., low- and high- states) by using the back gate (BG) bias. Our design utilizes the front gate (FG) and BG of an FDSOI FET as the input terminals and proposes the dynamic logic gates (like NAND, NOR, AND, OR, XOR, and XNOR) and circuits (like a half-adder and full-adder). It requires fewer transistors to build dynamic logic gates and achieves high performance with low power dissipation compared to conventional dynamic logic designs. The compact industrial model of FDSOI FET (BSIM-IMG) has been used to simulate dynamic logic gates and is fully calibrated to reproduce the 14 nm FDSOI FET technology node data. Calibration is performed for both electrical characteristics and process variations. The simulation results show an average improvement in transistor count, propagation delay, power, and power-delay product (PDP) of 23.43%, 57.16%, 47.05%, and 77.29%, respectively, compared to the conventional designs. Further, our design reduces the charge-sharing effect, which affects the drivability of the dynamic logic gates. In addition, we have analyzed the impact of the process, supply voltage, and load capacitance variations on the propagation delay of the dynamic logic family in detail. The results show that these variations have a minor impact on the propagation delay of the proposed FDSOI-based dynamic logic gates compared to the conventional dynamic logic gates
First demonstration of in-memory computing crossbar using multi-level Cell FeFET
No full textAdvancements in AI led to the emergence of in-memory-computing architectures as a promising solution for the associated computing and memory challenges. This study introduces a novel in-memory-computing (IMC) crossbar macro utilizing a multi-level ferroelectric field-effect transistor (FeFET) cell for multi-bit multiply and accumulate (MAC) operations. The proposed 1FeFET-1R cell design stores multi-bit information while minimizing device variability effects on accuracy. Experimental validation was performed using 28 nm HKMG technology-based FeFET devices. Unlike traditional resistive memory-based analog computing, our approach leverages the electrical characteristics of stored data within the memory cell to derive MAC operation results encoded in activation time and accumulated current. Remarkably, our design achieves 96.6% accuracy for handwriting recognition and 91.5% accuracy for image classification without extra training. Furthermore, it demonstrates exceptional performance, achieving 885.4 TOPS/W–nearly double that of existing designs. This study represents the first successful implementation of an in-memory macro using a multi-state FeFET cell for complete MAC operations, preserving crossbar density without additional structural overhead.14
Modeling and Benchmarking 5nm Ferroelectric FinFET from Room Temperature down to Cryogenic Temperatures
No full textThe rise in quantum-computing systems, space electronics, and superconducting processors requires compatible cryogenic memories. The stringent operating conditions for these applications put additional constraints on the endurance and reliable operation of such memories. Ferroelectric-Field Effect Transistors (FeFETs) based on ferroelectric properties of the Hafnium Zirconium Oxide (HZO) can be an excellent choice for these systems. This requires a thorough characterization of FeFET at deep cryogenic temperatures. Also, the scalability of the FeFET to lower technology nodes implies a lower area and reduced leakage. In this work, we, therefore, fully characterize the 5 nm node Fe-FinFET from 10 K to 400 K. To this end, the underlying 5 nm node FinFET transistor is calibrated with experimental data from cryogenic temperatures to above-room temperatures. The material parameters of the Ferroelectric layer are also calibrated with reported measurement data. We propose that the reported endurance improvement of the HZO layer at cryogenic temperatures can improve the reliability of the Fe-FinFET. The observed wake-up and fatigue at higher temperatures are also non-existent at cryogenic temperatures. Although the memory window is reduced at cryogenic temperature compared to room temperature, we can still hold multiple states. This is also verified through our simulations. Lastly, we demonstrate the variability in high and low threshold voltage states due to extrinsic variation sources of the underlying transistor and ferroelectric material parameters. We observe a relatively lower variation at cryogenic temperature.</p
Implementation of a decoder based on low-density parity-check code for 8 bit logical ALU
No full textDefying Temperature: Reliable Compute-in-Memory in Monolithic 3D using BEOL Ferroelectric TFT
No full textMonolithic 3D integration represents a major breakthrough in the quest for high-density, energy-efficient systems. Ferroelectric thin-film transistors (Fe-TFT) have garnered increasing attention due to their outstanding capability in realizing brain-inspired computing and compatibility with the back-end-of-the-line (BEOL) fabrication process. Nevertheless, monolithic 3D ICs inevitability suffer from excessive temperatures which degrade the device characteristics degrading the system performance. In this work, we are the first to demonstrate how existing Fe-TFT crossbar arrays can be employed to sense temperature and detect run-time thermal fluctuations. This enables the Fe-TFT array to self-adaptively adjust bias conditions and operate reliably for the entire temperature range. We demonstrate the proof-of-concept using meticulously calibrated device simulations and temperature measurements of fabricated BEOL Fe-TFT devices. Further, we perform an extensive device-to-system thermal modeling for Fe-TFT-based monolithic 3D ICs to (1) acquire accurate thermal maps, (2) assess the temperature's influence on the inference accuracy of deep neural networks, and (3) showcase the efficacy of our technique in defeating temperature effects
Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET
No full textSingle-port ferroelectric FET (FeFET) that performs write and read operations
on the same electrical gate prevents its wide application in tunable analog
electronics and suffers from read disturb, especially to the high-threshold
voltage (VTH) state as the retention energy barrier is reduced by the applied
read bias. To address both issues, we propose to adopt a read disturb-free
dual-port FeFET where write is performed on the gate featuring a ferroelectric
layer and the read is done on a separate gate featuring a non-ferroelectric
dielectric. Combining the unique structure and the separate read gate, read
disturb is eliminated as the applied field is aligned with polarization in the
high-VTH state and thus improving its stability, while it is screened by the
channel inversion charge and exerts no negative impact on the low-VTH state
stability. Comprehensive theoretical and experimental validation have been
performed on fully-depleted silicon-on-insulator (FDSOI) FeFETs integrated on
22 nm platform, which intrinsically has dual ports with its buried oxide layer
acting as the non-ferroelectric dielectric. Novel applications that can exploit
the proposed dual-port FeFET are proposed and experimentally demonstrated for
the first time, including FPGA that harnesses its read disturb-free feature and
tunable analog electronics (e.g., frequency tunable ring oscillator in this
work) leveraging the separated write and read paths.Comment: 32 page
Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET
No full textSingle-port ferroelectric FET (FeFET) that performs write
and read
operations on the same electrical gate prevents its wide application
in tunable analog electronics and suffers from read disturb, especially
in the high-threshold voltage (VTH) state
as the retention energy barrier is reduced by the applied read bias.
To address both issues, we propose to adopt a read disturb-free dual-port
FeFET where the write is performed on the gate featuring a ferroelectric
layer and the read is done on a separate gate featuring a nonferroelectric
dielectric. Combining the unique structure and the separate read gate,
read disturb is eliminated as the applied field is aligned with polarization
in the high-VTH state, thus improving
its stability, while it is screened by the channel inversion charge
and exerts no negative impact on the low-VTH state stability. Comprehensive theoretical and experimental validation
has been performed on fully depleted silicon-on-insulator (FDSOI)
FeFETs integrated on a 22 nm platform, which intrinsically has dual
ports with its buried oxide layer acting as the nonferroelectric dielectric.
Novel applications that can exploit the proposed dual-port FeFET are
proposed and experimentally demonstrated for the first time, including
FPGA that harnesses its read disturb-free feature and tunable analog
electronics (e.g., frequency tunable ring oscillator in this work)
leveraging the separated write and read paths
