1,721,017 research outputs found
Macromodel of CMOS operational amplifier including supply current variation
No full textA SPICE macromodel of a CMOS operational amplifier is described in which the supply current is modelled. This macromodel is suited to multilevel analogue fault simulation. The accuracy of the macromodel is demonstrated by comparison with the full transistor level model. A > 3 times increase in simulation speed compared with the full model is possible
Design for test technique for increasing the resolution of supply current monitoring in analogue circuits
No full textA design-for-test (DFT) technique for analogue circuits is proposed which splits all high current transistors into two. This technique reduces the fault-masking effects of the fault-free parts of the circuit, giving a potential fault cover of over 99%. Other advantages are the small area overhead and a low performance penalty.</p
Analogue fault modelling and simulation for supply current monitoring
No full textFault simulation of analogue circuits is a very CPU intensive task. This paper describes a technique to increase the speed of fault simulation. The effects of bridging faults within operational amplifiers have been classified according to the externally observable behaviour reducing the number of fault simulations by two thirds. Parameterisable macromodels have been written in which both fault-free specifications and faulty effects can be modelled. The supply current is also modelled. These macromodels have been verified by embedding within a larger circuit, and have been shown to accurately model fault-free and faulty behaviour, and to propagate faulty effects correctly. The macromodels simulate about 7.5 times faster than the full transistor model
Test Stimulus Generation for Steady-State Analysis of Analogue and Mixed-signal Circuits
No full text
A DFT technique to increase the resolution of AC RMS power supply current monitoring of complex analogue circuits
No full textRMS AC supply current monitoring with the addition of the novel DFT technique presented in this paper shows an increase in fault coverage for an embedded opamp from only 2.5% to over 70%. During a test, the effective width- length ratio of the transistors that draw the most AC current is reduced, causing the supply current drawn by other parts of the circuit that might be faulty to contribute relatively more to the overall supply current, allowing detection of faults. The results of Monte Carlo fault simulations demonstrate the principle. The most significant advantages of this DFT technique are increased fault coverage; small (1%) area overhead; and low impact on the performance of the circuit.</p
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