1,721,001 research outputs found
A very-olw-voltage frequency divider in folded MOS current mode logic with complementary n- and p-type flip-flops
No full textIn this article, a static frequency divider based on folded MOS current mode logic (FMCML) is presented. The design is based on alternating FMCML flip-flops with complementary pMOS or nMOS input differential pairs since common-mode problems arise by using only one type of FMCML flip-flops. The design is carried out after detailed theoretical modeling and analysis versus the flip-flop bias current, thus allowing defining optimized design strategies for the maximum speed or the minimum power-delay product (PDP). The frequency divider architecture and design strategies are validated considering a commercial 28-nm FDSOI CMOS technology. Postlayout simulations of a divider-by-16 show a maximum frequency of about 12 GHz with 74-μW power consumption for the high-speed design and a maximum frequency of 10 GHz with 53-μW power consumption for the minimum PDP design
A high-speed low-voltage phase detector for clock recovery from NRZ data
No full textA novel topology of phase detector (PD) for applications
in clock recovery systems from nonreturn-to–zero data is presented
in this paper. The PD operates directly on the data stream,
without requiring preprocessing, and behaves like a sampling-type
PD, providing a sinusoidal phase characteristic. The triple-tail cell
principle is exploited to obtain a circuit topology suitable to lowvoltage
high-speed applications, with a very simple structure and
thus limited jitter generation. A model is proposed to understand
circuit behavior and optimize its design. The PD has been used in
a clock-and-data recovery circuit for 10-Gb/s optical communications,
and measurements in agreement with SONET specifications
are reported
A revision of the theory of THz detection by MOSFET in the light of the self-mixing model
No full textCMOS technology has been extensively used for the realization of image sensors at Terahertz frequencies. The explanation of its strong efficiency was usually given invoking a mechanism described by the plasma wave detection theory. This model predicts that, when a high frequency potential is applied between gate and source electrodes of a MOSFET, oscillations of the 2D electron gas, located in the inversion layer, converts THz radiation into a DC voltage. Recently, we developed a new model of the self-mixing rectification process occurring in the depleted portion of a semiconductors crossed by a radiofrequency electric field. We studied both the new double barrier structure and the extensively used depleted region in MOS. In this paper, on the light of these new results, we review the theory of the THz detection in a MOS-FET structure. For a comparison with the former approach, we notice that the volume of interaction between free carriers and the RF electric field considered in this model is much higher that the volume considered in the plasma wave model. Technology Computer-Aided Design software simulations, using the Harmonic Balance analysis, will be adopted as evaluation tool. This consideration suggests that self-mixing effect may be more relevant in determining the rectification process. In the authors opinion, this approach substantially improves understanding of the THz rectification in semiconductors and in particular in MOS-FET structures
High-efficiency 0.3V OTA in CMOS 130nm technology using current mirrors with gain
No full textThis paper presents a novel ultra-low-power ultra-low-voltage operational transconductance amplifier (OTA). The OTA operates with a 0.3V supply voltage and shows remarkable bandwidth performance with very limited power consumption, owing to the use of current mirrors with gain. Low impedance internal nodes of the current mirrors allow to boost gain and bandwidth, adding only high-frequency poles to the frequency response. Therefore, the compensation of the proposed OTA can be achieved through a dominant pole at the output, as in conventional cascode amplifiers. The circuit employs two identical input stages with cross-coupled inputs to improve common-mode rejection ratio (CMRR) performance, and a differential-to-single-ended output stage. The resulting architecture achieves a remarkable FOMS value, as demonstrated by the simulations performed in a commercial 130nm CMOS technology
Low-power class-AB 4th-order low-pass filter based on current conveyors with dynamic mismatch compensation of biasing errors
No full textA 4th-order Butterworth class-AB current-mode low-pass filter is proposed, based on second-generation Current Conveyors (CCII). Class-AB operation allows high-power efficiency and driving large loads with small quiescent currents. The CCII topology uses the class-AB output buffer with error amplifiers: this topology is known to be sensitive to mismatch errors, which cause offsets in the error amplifiers, affecting the biasing current of the stage. This problem is solved via a control loop, which compensates the effect of mismatches. The technique is shown to be effective in Monte Carlo simulations with process variations and mismatches. Simulations have been carried out in 40 nm CMOS technology. The proposed filter achieves good power efficiency, thanks to the class-AB architecture, and good dynamic range, thanks to the closed-loop output buffer. A cut-off frequency of 6 MHz, with 184 μW of total quiescent power consumption, is achieved, with a THD of -55 dB and a SNR of 49 dB
Design of low-voltage power efficient frequency dividers in folded MOS current mode logic
Full text linkIn this paper we propose a methodology to design high-speed, power-efficient static frequency dividers based on the low-voltage Folded MOS Current Mode Logic (FMCML) approach. A modeling strategy to analyze the dependence of propagation delay and power consumption on the bias currents of the divide-by-2 (DIV2) cell is introduced. We demonstrate that the behavior of the FMCML DIV2 cell is different both from the one of the conventional MCML DFF (D-type Flip-Flop) and from FMCML DFF without a level shifter. Then an analytical strategy to optimize the divider in different design scenarios: maximum speed, minimum power-delay product (PDP) or minimum energy-delay product (EDP) is presented. The possibility to scale the bias currents through the divider stages without affecting the speed performance is also investigated. The proposed analytical approach allows to gain a deep insight into the circuit behavior and to comprehensively optimize the different design tradeoffs. The derived models and design guidelines are validated against transistor level simulations referring to a commercial 28nm FDSOI CMOS process. Different divide-by-8 circuits following different optimization strategies have been designed in the same 28nm CMOS technology showing the effectiveness of the proposed methodology
General approach to the calibration of innovative MFP multi-channel digitizers
No full textInnovative digitizers exploiting mixing, filtering and processing (MFP) operations can grant ultra-high bandwidth and sampling rate. Their operation combines analog processing stages with a digital signal processing stage, where massive operations are performed to obtain the digital representation of the input signal. In fact, the samples returned by the analog-to-digital converter (ADC) consist of a transformed, namely mixed and filtered, version of the input, which shall be processed in the digital domain to reconstruct the input signal. The digital processing is also designed to attain streamline calibration, which provides both the removal of non-ideal effects, such as mismatches between individual channels, and the improvement of the frequency response flatness. Calibration strategies represent an asset of manufacturers’ know-how, since the performance of the digitizer largely depends on the effectiveness of the calibration process. Gain equalization and aliasing removal are performed in the digital domain by finite impulse response (FIR) filtering of the ADCs’ outputs. A general method for the identification of the calibration filters, and their translation into algorithms for MFP digitizers using 2, 4, or any number of channels, is here proposed. Functional-level and circuit-level Cadence Virtuoso simulations in an STMicroelectronics Si-Ge heterojunction bipolar transistor (HBT) process are also carried out to evaluate the performance of the proposed method through a comparison between the digital representations of the signals obtained with and without calibration
A biasing approach to design Ultra-Low-Power Standard-Cell-Based Analog Building Blocks for Nanometer SoCs
Full text linkThis paper presents an approach to design analog building blocks for nanometer systems on a chip (SoCs) that are based on digital standard cells. The proposed approach guarantees that all the CMOS inverters, taken from a standard-cell library, operate with well-defined quiescent current and output voltage, thus allowing the implementation of analog circuits with good robustness against PVT variations. The approach is based on an Analog Body Bias Generator (ABBG) reusable block, similar to the ones adopted in digital applications to cope with process variations, and exploits the bulk terminals of both the p-channel and n-channel MOS transistors of the standard-cell inverter as current and voltage control inputs. The bulk voltages generated by the ABBG are routed to all the standard-cell inverters used for analog functions and allow to set the quiescent current of each cell to a multiple of a reference current and the static output voltage of each cell to half the supply voltage. The full custom design of the ABBG is presented, as well as the design flow to allow the automatic place and route of the proposed standard-cell based analog building blocks. We finally give an example of application to the design of a fully synthesizable four-stage-gain low-power operational transconductance amplifier (OTA). Both the body bias generator and the OTA have been implemented in a 65-nm CMOS technology. The OTA nominal current consumption is 1.75 μA with 0.41-μA standard deviation. Good robustness against supply and temperature variations is also found
An improved reversed miller compensation technique for three-stage CMOS OTAs with double pole-zero cancellation and almost single-pole frequency response
Full text linkThis paper presents an improved reversed nested Miller compensation technique exploiting a single additional feed-forward stage to obtain double pole-zero cancellation and ideally single-pole behavior, in a three-stage Miller amplifier. The approach allows designing a three-stage operational transconductance amplifier (OTA) with one dominant pole and two (ideally) mutually cancelling pole-zero doublets. We demonstrate the robustness of the proposed cancellation technique, showing that it is not significantly influenced by process and temperature variations. The proposed design equations allow setting the unity-gain frequency of the amplifier and the complex poles' resonance frequency and quality factor. We introduce the notion of bandwidth efficiency to quantify the OTA performance with respect to a telescopic cascode OTA for given load capacitance and power consumption constraints and demonstrate analytically that the proposed approach allows a bandwidth efficiency that can ideally approach 100%. A CMOS implementation of the proposed compensation technique is provided, in which a current reuse scheme is used to reduce the total current consumption. The OTA has been designed using a 130-nm CMOS process by STMicroelectronics and achieves a DC gain larger than 120 dB, with almost single-pole frequency response. Monte Carlo simulations have been performed to show the robustness of the proposed approach to process, voltage, and temperature (PVT) variations and mismatches
An E-band variable gain amplifier with 24 dB-control range and 80 to 100 GHz 1 dB bandwidth in SiGe BiCMOS technology
No full textAnalysis, design, and characterization of an E-band Variable Gain Amplifier (VGA) in SiGe BiCMOS commercial technology is presented. VGA topologies are compared in terms of their capability to contribute to receiver linearity and dynamic range. The proposed VGA is based on a Gilbert multiplier cell exploiting current cancellation to enhance control range and linearity. A 1 dB bandwidth ranging from 80 to 100 GHz, a 24 dB gain control range and a -11.5 dBm input 1 dB compression point have been measured
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