1,722,093 research outputs found
A 2GS/s 10-bit time-interleaved capacitive DAC for self-interference-cancellation application
No full textThis article presents a 2-GS/s time-interleaved (TI) 10-bit capacitive digital-to-analog converter (CDAC) for self-interference-cancellation (SIC) application. It is also capable of working as a non-TI & stand-alone CDAC with 1-GS/S clock frequency. By taking advantage low parasitic capacitance and equivalent parasitic capacitance at bottom and top plate of MIM capacitor, the split-capacitor technique is used without significant degradation in the linearity. The special architecture of the designed layout also relieves the local and radial oxide gradient error. The CDAC is designed in 28nm CMOS technology. If the CDAC works in stand-alone mode with 1-GS/s clock frequency, followed by an additional anti-aliasing filter and the baseband input frequency equals 10.74 MHz, the ENOB, SFDR and THD at the output of the filter is equal to11.3-bit,76 dB and 76dB, respectively
A 140-μW Front-End with 5.7-dB NF and +10-dBm OOB-IIP3 Using Voltage-Mode Boosting Mixer
No full textThis letter proposes an ultralow-power mixer-first front-end using voltage-mode boosting. The voltage gain is achieved passively by using capacitive stacking. By employing N-path filtering technique, this front-end achieves high out-of-band (OOB) rejection which results in high in/OOB linearity. A prototype, composed of four-paths with six stages of switched capacitors, is fabricated in 28-nm CMOS technology, and achieves 29-dB gain, 5.7-dB noise figure (NF) and +10-dBm OOB-IIP3 while consuming less than 140μW
A 1.5–2.8 GHz current-mode LNTA achieving >25 dBm IIP3 and +8 dBm P-1dB gain compression
No full textTo meet the requirements of future SAW-less frequency-division duplexing (FDD) and phased-array receivers, the linearity of the Low-Noise Transconductance-Amplifier (LNTA) should be considerably improved. In this paper, a highly-linear common-gate (CG) amplifier is presented that can be directly connected to the antenna. The LNTA operates in current-mode and is not power-matched to the antenna. In this way, noise and distortion of the active devices are strongly suppressed. Optimum LNTA driving impedance is provided by a transformer-based LC resonant network, while the LNTA core consists of a complementary cross-coupled CG stage to save power. The impact of passive losses is minimized using the noise-matching technique. Furthermore, the effect of source impedance variation on IIP3, NF and gain is also investigated. The measured IIP3 of the LNTA is more than 25 dBm from 1.5 to 2.8 GHz. The P-1dB gain compression is also +8 dBm. The chip is implemented in 28 nm CMOS and has an active area of 0.29 mm(2) and draws only 8 mA from a 1.8 V supply
A 17 mW 33 dBm IB-OIP3 0.5-1.5 GHz Bandwidth TIA Based on an Inductor-Stabilized OTA
No full textA highly linear Trans-Impedance Amplifier (TIA) for 5G New Radio mobile communication receivers is presented. The TIA has a cut-off frequency programmable from 500 MHz up to 1.5 GHz. The TIA is based on a Feed-Forward compensated amplifier. To ensure stability while achieving high bandwidth and low power, an inductor is used inside the feed-forward stage. A test chip has been realized in 28 nm CMOS technology. The TIA achieves an In-band O1P3 of 32.9 dBm and the output integrated noise from 20 MHz to 1.5 GHz is lower than 300 mu V-rms with a power dissipation of 17 mW
A Sub-1V, 220 μw Receiver Frontend for Wearable Wireless Sensor Network Applications
No full textMinimizing the dissipated power of RF transceivers is the primarily target to meet the requirements of wearable wireless sensor networks (W-WSN). This paper presents an Ultra-Low Power (ULP) receiver with RF performance exceeding the requirements of the intended application. Thanks to the highly efficient current-reuse Low Noise Amplifier (LNA), followed by a passive mixer, the single-ended 2.4 GHz RF input is down-converted to a low-IF. To generate 25% quadrature LO signals, a high-swing complementary current-reuse Class-C VCO, operating at twice the desired frequency, is followed by a frequency divider-by-two. Furthermore, complex channel selection filtering with center frequency and passband of 2 MHz and 1 MHz respectively is performed utilizing the Gm-boosted Common-Gate baseband stage immediately following the mixer. The proposed receiver is designed and simulated in 40 nm CMOS technology. The entire receiver consumes only 220 μW from 0.8 V supply voltage. It shows DSB-NF of 7.5 dB, conversion gain of 50 dB and image rejection of 20 dB. The proposed design represents almost two times better power efficiency with respect to the state-of-the-art with better or equal RF performance
A 2nd order current-mode filter with 14dB variable gain and 650MHz to 1GHz tuning-range in 28nm CMOS
No full textAn open-loop baseband filter with bandwidth of 1GHz suitable for a receiver operated in the 5G high frequency band (above 24GHz) is presented. The filter is based on a gain boosted Common Gate topology that implements a 2nd order low-pass filter in the current domain. A frequency-dependent active negative capacitance circuit is used to boost the quality factor of the filter. This not only improves in-band flatness but also increases out-of-band selectivity. A test chip has been realized in 28nm CMOS technology. The filter bandwidth can be programmed from 650 MHz to 1 GHz and the current gain changed by 14 dB, with the power dissipation scaling from 11 mW to 5 mW. In-band IIP3 is +2 dBm and the input noise integrated from 10 MHz to 1 GHz is lower than 170 μVrms
A 260-MHz RF Bandwidth Mixer-First Receiver with Third-Order Current-Mode Filtering TIA
No full textA mixer-first wideband receiver with RF bandwidth of 260 MHz suitable for the 5G lower frequency band (below 6 GHz) is presented. The filtering trans-impedance amplifier immediately following the mixer is based on a regulated cascode, instead of a conventional shunt-feedback architecture. Thanks to a positive-feedback capacitance multiplication, third-order low-pass filtering in the current domain is performed. Wide bandwidth, high linearity, and low power are thus achieved. Measurements on a 28-nm CMOS chip prototype show alternate channel IIP3 and P1dB of +22 dBm and +3 dBm, respectively. RX NF is 5.5 dB while power consumption is 21.6 mW (signal path) and 7.8-mW/GHz (LO) with 1.8/1.2-V supply
A 17-mW 0.5-1.5-GHz Bandwidth TIA Based on an Inductor-Stabilized OTA with 35-42-dBm In-Band IIP3
No full textA transimpedance amplifier (TIA) is presented for 5G and future mobile standards. The bandwidth of the TIA can be programmed from 500 MHz to 1.5 GHz. The operational transconductance amplifier (OTA) is designed combining feedforward compensation and inductive peaking, to ensure loop stability and obtain high loop gain with low-power dissipation. TSMC 28-nm HPC technology was used to implement a test chip. With a power dissipation of 17 mW, the TIA achieves an in-band IIP3 ranging from 35 to 42 dBm and output integrated noise of 300 μ Vrms
A 58 GHz Bandwidth, and less than 1.8% THD, Mach-Zehnder Driver, in 28 nm CMOS Technology
No full textThis work presents a linear Mach-Zenlider modulator driver. The key features of this design are a distortion which goes with the inverse of the input amplitude and a wide bandwidth. The two things make the reported driver suitable for Coherent Optical Applications. The mainstream technology for these applications is BiCMOS, however, in this case, a 28 nm CMOS technology has been used, aiming for higher integration level and lower cost. The resulting Total Harmonic Distortion (THD) for 1.5 V peak-to-peak differential output swing is always below 1.8%, with a -3 dB bandwidth of 58 GHz. The complete transmitter provides gain ranging from 10 dB to 20 dB in a continuous way. The overall power consumption at 20 dB is 297 mW, with a single supply voltage of 2.4 V
Sorting the wheat from the chaff in macroprolactinaemia assessment.
No full textSorting the wheat from the chaff in macroprolactinaemia assessment; lette
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