1,720,974 research outputs found
Software Energy Estimation Based on Statistical Characterization of Intermediate Compilation Code
No full textEarly estimation of embedded software power consumption is a critical issue that can determine the quality and, sometimes, the feasibility of a system. Architecture-specific, cycle accurate simulators are valuable tools for fine-tuning performance of critical sections of the application but are often too slow for the simulation of entire systems. This paper proposes a fast and statistically accurate methodology to evaluate the energy performance of embedded software and describes the associated
toolchain. The methodology is based on a static characterization
of the target instruction set to allow estimation on an equivalent,
target-independent intermediate code representation
Performance/reliability trade-off in superscalar processors for aggressive NBTI restoration of functional units
No full textNegative-Bias Temperature Instability has become a serious reliability concern in modern processors design, and in the last decade many research effort has been spent in developing circuit-level and architecture-level strategies to mitigate the induced delay variation of nanoscale circuits. At the architecture level, work has been proposed to alleviate this by appropriate dynamic instruction schedulingntechniques. However, their benefit is bounded to the available redundancy, limiting their attractiveness for a cost-effective VLSI solution. This paper presents an in-depth analysis of a performance reliability trade-off FSM design, that is able to attain the desired level of reliability improvement according to the ILP performance constraints. Power-gating is used for aggressive NBTI restoration. Extensive experimental results show several performance reliability trade-off examples in a broad range of application scenarios
Estimation of thermal status in multi-core systems
No full textModern multi-core architectures are prone to a complex dynamic thermal management process: the presence of multiple cores adds challenges to the temperature estimation activity, due to the induced heat-up process from adjacent cores. Run-time estimation can benefit from floorplan information to better estimate the thermal characteristics of each core, and transient information can help the system to predict and avoid thermal alarms, increasing the system reliability and lifetime. In this context, the present work aims at defining a novel on-line measurement methodology based on neighbor nodes and transient information, providing a metric to be employed in thermal-aware designs, either at design-time to characterize application and platform from a thermal view-point, or at run-time in conjunction with the Dynamic Thermal Management subsystem. The proposed methodology intercepts floorplan-induced thermal behavior that would be otherwise unrecognized, and it also shows how a non-floorplan-aware methodology can reveal up to a
30% error in the estimate of thermal status
NBTI Mitigation in Microprocessor Designs
No full textNegative-Bias Temperature Instability seriously affects nanoscale circuits reliability and performance. Continuous stress and increasing operating temperatures lead to device degradation and long-term system unavailability. The opportunity to optimize the duty-cycle of the stress/recovery phases to reduce Vth degradation leads to innovative research of reliability-oriented resources allocation at architectural level. This work explores the impact of different allocation strategies on the processor degradation, through a novel estimation methodology. Experimental results show that the proposed NBTI-aware allocation strategy can guarantee from 10% and up to 30% lower degradation compared to classical strategies, under different operating scenarios and under process variability
Thermal/performance trade-off in network-on-chip architectures
Full text linkMulti-core architectures are a promising paradigm to exploit the huge integration density reached by high-performance systems. Indeed, integration density and technology scaling are causing undesirable operating temperatures, having net impact on reduced reliability and increased cooling costs. Dynamic Thermal Management (DTM) approaches have been proposed in literature to control temperature profile at run-time, while design-time approaches generally provide floorplan-driven solutions to cope with temperature constraints. Nevertheless, a suitable approach to collect performance, thermal and reliability metrics has not been proposed, yet. This work presents a novel methodology to jointly optimize temperature/performance trade-off in reliable high-performance parallel architectures with security constraints achieved by workload physical isolation on each core. The proposed methodology is based on a linear formal model relating temperature and duty-cycle on one side, and performance and duty-cycle on the other side. Extensive experimental results on real-world use-case scenarios show the goodness of the proposed model, suitable for design-time system-wide optimization to be used in conjunction with DTM technique
Heterogeneous Architectures and Networks-on-Chip Design and Simulation
No full textIn current multi-core scenario, Networks-on-Chip (NoC) represent a suitable choice to face the increasing communication and performance requirements, however introducing additional design challenges to already complex architectures. In this perspective, there is a need for flexible and configurable virtual platforms for early-stage design exploration. We present the Heterogeneous Architectures and Networks-on-Chip Design and Simulation framework for large-scale high-performance computer simulation, integrating performance, power, thermal and reliability metrics under a unique methodology. Moreover, NoC exploration is possible from a reliability/performance and thermal/performance trade-offs. © 2012 ACM
A Temperature and Reliability Oriented Simulation Framework for Multi-core Architectures
Full text linkThe increasing complexity of multi-core architectures demands for a comprehensive evaluation of different solutions and alternatives at every stage of the design process, considering different aspects at the same time. Simulation frameworks are attractive tools to fulfil this requirement, due to their flexibility. Nevertheless, state-of-the-art simulation frameworks lack a joint analysis of power, performance, temperature profile and reliability projection at system-level, focusing only on a specific aspect. This paper presents a comprehensive estimation framework that jointly exploits these design metrics at system-level, considering processing cores, interconnect design and storage elements. We describe the framework in details, and provide a set of experiments that highlight its capability and flexibility, focusing on temperature and reliability analysis of multi-core architectures supported by Network-on-Chip interconnect
Exploiting Thermal Coupling Information in MPSoC Dynamic Thermal Management
No full textTemperature profile optimization is one of the most relevant and challenging problems in modern multi-core architectures. Several Dynamic Thermal Management approaches have been proposed in literature, and run-time policies have been designed to direct the allocation of tasks according to temperature constraints. Thermal coupling is recognized to have a role of paramount importance in determining the thermal envelope of the processor, nevertheless several works in literature do not take directly into account this aspect while determining the status of the system at run-time. Without this information, the DTM design is not able to fully redistribute the roles that each core have on the system-level temperature, thus neglecting important information for temperature-constrained workload allocation.
Purpose of this work is to provide a novel mechanism to better support DTM policies, focusing on the estimation of the impact of thermal coupling in determining the appropriate status from a thermal stand-point. The presented approach is based on two stages: off-line characterization of the target architecture estimates thermal coupling coefficients, that will be used at run-time for proper DTM decisions
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