1,720,978 research outputs found
Influence of dielectric breakdown on MOSFET drain current
No full textBreakdown of gate dielectric is one of the most dangerous threats for reliability of MOSFET devices in operating conditions. Not only the gate leakage resulting from breakdown is a problem for power consumption issues, but the "on" drain current can be strongly affected. In this paper, we show that in recent technologies, featuring ultrathin gate dielectrics, the corruption of drain current due to breakdown can be modeled as the effect of a portion of channel being damaged by the opening of the breakdown spot. Devices featuring 2.2- and 3.5-nm-thick gate oxide and various channel widths are stressed by using a specialized setup, and the degradation of transistor parameters is statistically studied. The analysis shows that the radius of the damaged region responsible for drain current degradation can be estimated between 1.4 and 1.8 /spl mu/m
Depassivation of Latent Plasma Damage in n-MOSFETs
No full textIndispensable in CMOS manufacturing, plasma treatments may result in a latent damage in gate oxides. We propose a method to detect this latent damage as a function of the area of the multifingered metal pad connected to the gate, by using an experimental method based on constant current stress and oxide trapped charge measurements. We measured a power law behavior describing the dependence of the trapped charge on the injected charge
Dosimetry method for use in treatment of brain tumor, involves determining changes in threshold value of cells which are exposed to ionizing radiation by correlating address of cell to corresponding position in two-dimensional array
No full textNOVELTY - The threshold value written cells of flash memory (12) are exposed to ionizing radiation and the state of the cells are read to calculate the absorbed dose. Address of each memory cell is correlated to corresponding position in a two-dimensional array and the changes in the threshold value of cells are determined.
USE - Dosimetry method for use in treatment of brain tumor. Can also be used for security systems, sterilization application, high energy physics, space applications and medical applications.
ADVANTAGE - Since changes in threshold value of cells which are exposed to ionizing radiation are determined by correlating address of each cell to corresponding position in two-dimensional array, ensures possibility of delivering very high dose to tumor without destroying the surrounding tissue. Thus the spatial resolution of the dosimeter is improved
RF-MEMS Switches Reliability for Long Term Spatial Applications
No full textOhmic RF-MEMS switches have been fully characterized regarding their robustness to Electro-Static Discharge events (ESD), Total
Ionizing dose (TID) radiation, and long term actuation, obtaining important guidelines to improve the reliability of such devices. These tests,
although very important for a complete device qualification for spatial applications, are in fact poorly investigated in literature
Plasma induced damage from via etching in pMOSFETs
No full textIn this paper, we present a study of micro breakdown (MB), soft breakdown (SB), and conventional hard breakdown (HB) on pMOSFET devices. In particular, we report evident damage due to via etching
Impact of total dose on heavy-ion upsets in floating gate arrays
No full textWe studied the impact of previous X-ray irradiation on the sensitivity of floating gate cells to heavy-ion upsets, to emulate the concurrent occurrence of both total ionizing dose and single event effects in the space environment. An increasing heavy-ion upset cross section for increasing total dose was measured, especially with low-LET particles, where the enhancement can be bigger than one order of magnitude. We attributed this behaviour to the combination of the threshold voltage shifts induced by X-rays and heavy ions
Error Instability in Floating Gate Flash Memories Exposed to TID
No full textWe discuss new experimental results on the post-radiation annealing of Floating Gate errors in Flash memories with both NAND and NOR architecture. We investigate the dependence of annealing on the program level, linking the reduction in the number of Floating Gate errors to the evolution of the threshold voltage of each single cell. To understand the underlying physics we also discuss how temperature affects the number of Floating Gate errors
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