1,721,090 research outputs found
Optimality Assessment of Memory-Bounded ConvNets Deployed on Resource-Constrained RISC Cores
Full text linkThe Human Brain Project and neuromorphic computing
Full text linkUnderstanding how the brain manages billions of processing units connected via kilometers of fibers and trillions of synapses, while consuming a few tens of Watts could provide the key to a completely new category of hardware (neuromorphic computing systems). In order to achieve this, a paradigm shift for computing as a whole is needed, which will see it moving away from current “bit precise” computing models and towards new techniques that exploit the
stochastic behavior of simple, reliable, very fast,
low-power computing devices embedded in intensely recursive architectures. In this paper we summarize how these objectives will be pursued in the Human Brain Project
TVFS: Topology Voltage Frequency Scaling for Reliable Embedded ConvNets
Full text linkThis brief introduces Topology Voltage Frequency Scaling (TVFS), a performance management technique for embedded Convolutional Neural Networks (ConvNets) deployed on low-power CPUs. Using TVFS, pre-trained ConvNets can be efficiently processed over a continuous stream of data, enabling reliable and predictable multi-inference tasks under latency constraints. Experimental results, collected from an image classification task built with MobileNet-v1 and ported into an ARM Cortex-A15 core, reveal TVFS holds fast and continuous inference (from few runs, up to 2000), ensuring a limited accuracy loss (from 0.9% to 3.1%), and better thermal profiles (average temperature 16.4 °C below the on-chip critical threshold)
TentacleNet: A Pseudo-Ensemble Template for Accurate Binary Convolutional Neural Networks
Full text linkBinarization is an attractive strategy for implementing lightweight Deep Convolutional Neural Networks (CNNs).
Despite the unquestionable savings offered, memory footprint above all, it may induce an excessive accuracy loss that prevents a widespread use. This work elaborates on this aspect introducing TentacleNet, a new template designed to improve the predictive performance of binarized CNNs via parallelization. Inspired by the ensemble learning theory, it consists of a compact topology that is end-to-end trainable and organized to minimize memory utilization. Experimental results collected over three realistic benchmarks show TentacleNet fills the gap left by classical binary models, ensuring substantial memory savings w.r.t. state-of-theart binary ensemble methods
Tunable Error Detection-Correction for Efficient Adaptive Voltage Over-Scaling
No full textThis work introduces a Tunable Error Detection & Correction strategy (TED-C) aimed at improving the efficiency of adaptive voltage over-scaling (AVOS) in error-resilient applications. Through TED-C, the error coverage can be adjusted at run-time in order to accelerate the voltage scaling and achieve ultra-low energy consumption at the cost of quality-of-result (QoR). The mechanism is built upon elastic timing monitors, i.e., standard Razor-based timing monitors augmented with a tunable detection window and hardened with the aid of a dynamic short-path padding technique. Results collected over a FIR filter simulated with different realistic audio streams show TED-C achieves ultra-low energy-per-operation (up to 49.7% savings w.r.t. a standard Razor-driven AVOS) with negligible area overhead (2.4% vs. 27.5%) and low QoR degradation (0.72%)
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