54 research outputs found
Machining of titanium alloys with coated and uncoated carbide tools
No full textSIGLEAvailable from British Library Document Supply Centre-DSC:DXN020620 / BLDSC - British Library Document Supply CentreGBUnited Kingdo
Experimental analysis of design-for-testability techniques in SRAMs
No full textIn this thesis the importance of DFTs in the detection of DRFs in embedded SRAMs have been presented. To illustrate their importance an accurate SRAM simulation model has been build. This model was used in the implementation of some existing DFT techniques. The proposed SRAM simulation model includes all peripheral circuits but for the timing generation circuit and the data input and output latch. The advantage of this simulation model is that the model can be used for any simulation purpose concerning memory faults in SRAMs. The addition of the address decoder logic was due to the fact that, the address decoder is necessary when multiple cells has to be accessed in parallel by selecting the appropriate wordlines. This model thus presents a complete analog behavior of an SRAM circuit. However the additional address decoder logic also increases the delay of the SRAM to a greater extend. The evaluation of the WWTM, NWRTM and PDWTM DFT techniques have also provided some data as to how efficient these DFT techniques are thereby easing some design decision as to which DFTs can used in the detecting DRFs in the cell array. Since two of these DFT were proven to detect symmetric and asymmetric faults within a reduced test time, they could be used as standards for the evaluation of other exiting and new DFT techniques. The PDWTM DFT was not validated. However we could not based on the obtained results to draw conclusions. Futher simulations should be carried out. Functional tests most specifically the Pause test was shown to be an inefficient test method in the detection of DFRs since the pause time is very long and not known for small R-values. Using DFTs thus reduces the pause time to a greater extend. DFTs are the most preferred test methods for the detection of DRFs. However the efficiency of any DFT for the detection of DRFs can only be justified if it can detect both symmetric and asymmetric defects, as was the case with two of the DFTs evaluated.Electrical Engineering, Mathematics and Computer Scienc
Experimental Analysis on ECC Schemes for Fault-Tolerant Hybrid Memories
No full textHybrid memories are one of the emerging memory technologies for future data storage. These memories are structured by integrating non-CMOS nanodevices (e.g., carbon nanotubes, single electron junction, organic molecules) with CMOS devices. Non-CMOS nanodevices build up crossbar-based memory cells, whereas CMOS devices form peripheral circuits. CMOS/Molecular (CMOL) memory is an example of hybrid memories. In spite of providing a huge data capacity and low power consumption, such memories suffer from high degree of cluster faults impacting their reliability. This thesis investigates the use of error correction codes (ECCs) to tolerate faults in hybrid memories. The ECCs considered in this work are Hamming, Reed Solomon (RS), and Redundant Residue Number System (RRNS) codes. The error correction capability and the cost incurred (in terms of area and time overhead of encoder and decoder) for each ECC and for different input data width are analyzed. The experimental results show that RS and RRNS codes are able to correct cluster faults, yet requires higher cost as compared to Hamming code, which can only correct single fault at lower cost. Moreover, the area cost of RS and RRNS encoder/decoder tend to increase linearly and exponentially, respectively, as the input data width becomes bigger. Meanwhile, the time overhead of RS remains steady and while that of increases linearly, as the input data width increase. Overall, RS is the best ECC to tolerate cluster faults in hybrid memories.Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Testability and Fault Tolerance for Emerging Nanoelectronic Memories
No full textEmerging nanoelectronic memories such as Resistive Random Access Memories (RRAMs) are possible candidates to replace the conventional memory technologies such as SRAMs, DRAMs and flash memories in future computer systems. Despite their advantages such as enormous storage capacity, low-power per unit device and reduced manufacturing difficulties, these emerging memories are expected to suffer from high manufacturing defect densities (reducing their quality) and in-field fault rates including clustered faults (reducing their reliability). These defects and faults may occur in any part of the memory system including the memory cell array, peripheral circuits and interconnects. Therefore, developing appropriate schemes to address both quality and reliability challenges is critical for the manufacturability of such devices. This thesis discusses the quality and reliability improvement for nanoelectronic memories. In order to develop effective schemes for quality improvement, first a framework of possible defects within RRAMs has been defined. Thereafter, defect injection and circuit simulation using an electrical RRAM model have been performed. Besides conventional memory faults, simulation results also show the occurrence of unique faults. The detection of the latter faults cannot be guaranteed with conventional memory test approaches as read operations will produce random values. Therefore, Design-for-Testability (DfT) schemes have been introduced to increase the fault/defect coverage at minimum overhead. In addition, as the faults may behave differently subject to process variations, the DfT schemes are made programmable to track the changes in fault behaviors while targeting the unique faults. On the other hand, several fault-tolerant (FT) schemes have been proposed to improve the in-field reliability of nanoelectronic memories. First, two FT schemes based on error correction codes (ECCs) have been introduced to tolerate both random and clustered faults in the memory cell array, while optimizing the area overhead and performance penalty. Second, an on-line masking scheme is combined with one of the proposed FT schemes to tolerate faults both in the decoders and the memory array; the decoding process has been modified realizing even smaller and faster decoding circuit. Third, an interleaving scheme is combined with an ECC to tolerate faults in the interconnects at minor area overhead and performance penalty.Microelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Message from the Chief Editor
Full text linkWelcome to the Second Issue of International Journal of Engineering Science and Technology Development (IJEST) on August 2013. In this issue of IJEST, we present to our readers selected articles related to Engineering, Science and Computer and Tehnology. Five papers are presented from Indonesia, Malaysia, Japan and Australia.The first article by Dr. Wamiliana from Lampung University, Indonesia and Prof. Dr. Louis Caccetta from Curtin University of Technology, Australia with the title: The Modified CW1 Algorithm For The Degree Restricted Minimum Spanning. The second article by Dr. Ibrahim, G.A., Arinal, H., from Lampung University, Indonesia and Zulhanif from National Univerisity of Malaysia, Malaysia and Haron,C.H.C from University Kebangsaan Malaysia with the title: Microstructure Alterations of Ti-6Al-4V ELI during Turning by Using Tungsten Carbide Inserts under Dry Cutting Condition. The third article by Dr. Rudi Irawan, Dr. Afzeri Tamsir and Dr. Riza Muhida from Surya University, Indonesia with the title: Indonesia’s Challenge to Combat Climate Change Using Clean Energy. The fourth article by Fritz Akhmad Nuzir, Haris Murwadi from Universitas Bandar Lampung, Indonesia and Prof. Bart Julien Dewancker from University of Kitakyushu, Japan with the title: The Importance of Education Facility as Sustainable Urban Generation Tool. The fifth article by Marzuki, Agus Sukoco, Lisa Devilia and Maria Shusanti F from Bandar Lampung University, Indonesia with the title: Analysis Web-Education Based on ISO/IEC 9126-4 for the Measurement Quality of Use.With these selections I sincerely hope that everyone has something to gain from this issue and thank you to article contributors and reviewers for making this issue possible. To all prospective author, we are welcome and please sent your article to the editors
The innovation of Labu Sayong manufacturing technology: a technical analysis
No full textLabu Sayong or also known as Labu Picit (pinched clay pitcher) is one of Malay potteries craft heritage originated from the state of Perak. This hand-crafted work has the specialties of its own. The stored water in the clay pitcher is colder than usual and it is believed that the water can refresh the body when consumed. Labu Sayong is an adaptation of a gourd and served as a symbol of intellectuals of the Malays in the past. It is produced through several traditional processes in stages and it takes some time to complete. This factor may cause its extinction. Therefore, many entrepreneurs have switched to a new innovation in the manufacturing process. Now, Labu Sayong has been produced by using moulds and it is called Labu Acu or cast clay pitcher. This innovation can produce commercialized product and the process is more productive than the traditional ways. To take these matters into consideration, the author used qualitative research method by using cultural approach in collecting written or visual data such as interviews and observation. An analysis of the technical aspects has found that the casting technique has successfully improved the quality and quantity of Labu Sayong which meets market demands. It is hoped this paper will give a certain amount of knowledge and facts that the manufacturing process of Labu Sayong is now going through a technological innovation. Innovation is crucial to ensure that Malay heritage will continue to exist and will never lost in the advanced technological era
Skeleton-based design and simulation flow for Computation-in-Memory architectures
No full textMemristor-based Computation-in-Memory is one of the emerging architectures proposed to deal with Big Data problems. The design of such architectures requires a radically new automatic design flow because the memristor is a passive device that uses resistance to encode its logic value. This paper proposes a design flow for mapping parallel algorithms on the CIM architecture. Algorithms with similar data flow graphs can be mapped on the crossbar using the same template containing scheduling, placement, and routing information; this template is named skeleton. By configuring such a skeleton with different pre-designed circuits, we can build CIM implementations of the corresponding algorithms in that class. This approach does not only map an algorithm on a memristor crossbar, but also gives an estimation of its performance, area, and energy consumption. It also supports user-defined constraints and parallel SystemC simulation. Experimental results demonstrate the feasibility and the potential of the approach.Accepted Author ManuscriptComputer EngineeringQuantum & Computer EngineeringFTQC/Bertels La
Flank wear and I-kaz 3D correlation in ball end milling process of Inconel 718
Full text linkTool wear may deteriorate the machine product quality due to high surface roughness, dimension exceeding tolerance and also to machine tool itself. Tool wear monitoring system is vital to be used in machining process to achieve high quality of the machined product and at the same time improve the productivity. Nowadays, many monitoring system developed using various sensor and statistical technique to analyze the signals being used. In this paper, I-kaz 3D method is used to analyze cutting force signal in milling process of Inconel 718 for monitoring the status of tool wear in milling process. The results from analyzing cutting force show that I-kaz 3D coefficient has a correlation with cutting tool condition. Tool wear will generate high value of I-kaz 3D coefficient than the sharp cutting tool. Furthermore, the three dimension graphical representation of I-kaz 3D for all cutting condition shown that the degree of scattering data increases with tool wear progression
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