1,721,152 research outputs found
Message from the Editor-in-Chief
No full textPresents the introductory editorial for this issue of the publication
Safety and Resiliency Challenges for Highly Autonomous Intelligent Systems
No full textIntelligent systems, capable of taking autonomous decisions based on AI algorithms, are becoming more and more widespread in several application fields (autonomous robots, autonomous vehicles, smart factories, smart agriculture, etc.). This thanks to their possible adoption to replace and/or collaborate with humans in harsh environments (hospitals, mines, space, etc.) and/or in difficult jobs (goods delivery, surveillance, etc.). Moreover, autonomous robots (e.g., service robots) and vehicles (e.g., drones) are today’s receiving an increasing interest, due to their possible pivotal role in facing the current pandemic emergency and its aftermath. They are complex systems, requiring intelligence at the edge (for low-latency data acquisition and processing), in the network, and up to the cloud and related services. Since such autonomous intelligent systems are in a closed collaboration with human beings and/or the health of human beings may depend on their operation, the need to guarantee their functional safety and resiliency with respect to hazardous conditions emerges. Enabling to increase the autonomy level of such intelligent systems, thus moving towards a smarter world, mandates to satisfy stronger requirements in terms of their functional safety and resiliency. Safety and resiliency challenges to enable highly autonomous intelligent systems are discussed
Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-Checking Circuits
No full textIn this paper we propose signal coding and CMOS gates that are suitable to self-checking circuits with combinational functional blocks implemented also by next generation, very deep submicron technology. In particular, our functional blocks satisfy the Strongly Fault-Secure property with respect to a wide set of possible, internal faults including not only conventional stuck-ats, but also transistor stuck-ons, transistor stuck-opens, resistive bridgings, delays, crosstalks and transient faults, that are very likely to affect next generation ICs. Compared to alternative, existing solutions, that proposed here does not imply any critical constraint on the circuit electrical parameters. Therefore, it is suitable to be adopted to design very deep submicron self-checking circuits which, compared to todays' circuits, will present significantly increased sensitivity to parameter variations occurring during fabrication
Testing Resistive Opens and Bridging Faults Through Pulse Propagation
No full textAbstract
This paper addresses the problems related to resistive opens and bridging faults that lie out of the most critical paths. These faults cannot be detected by traditional delay fault testing because the induced delay defects are not large enough to result in timing violations when the test rate is equal to the nominal operating frequency. In spite of this problem, resistive opens and bridgings should be detected because they may give rise to reliability problems. To detect them, we propose a testing method that is based on the propagation of pulses within the faulty circuit and that exploits the degraded capability of faulty paths to propagate pulses. The effectiveness of our method is analyzed at the transistor level and compared with the use of reduced clock periods to detect the same class of faults. Results show similar performance in the case of resistive opens and better performance in the case of bridgings. Moreover, the proposed approach is not affected by possible problems in the clock distribution
Special Section on Emerging Trends and Design Paradigms for Memory Systems and Storage
No full textWelcome to all readers of this special section addressingchallenges and innovative design and implementation strate-gies for memory systems and storage.As is well-known, the continued scaling of silicon-basedmicroelectronics technology, as well as the emergence ofnew, non-silicon-based technologies, enable increasingsystem complexity and performance, paving the way forapplications that had been unthinkable a few years ago. Atthe same time, increasingly diverse Internet of Things (IoT)applications and Autonomous Intelligent Systems demandthat an ever-increasing amount of data be correctly and rap-idly stored and accessed, posing new challenges to memorysystems and storage elements.In this special section we address issues related to design,test, reliability, resilience and availability of memory systemsand storage
Low-Cost Strategy for Bus Propagation Delay Reduction
No full textWe propose a strategy to reduce the propagation delay of microprocessors’ digital bus lines at very low costs in terms of area overhead, power consumption and power-delay product. Likewise some solutions adopted in industry nowadays, our strategy inserts in the bus lines repeaters implemented as a chain of inverters with increasing size. In this paper, we derive new expressions to determine the optimum number of inverters to be used within each repeater, and the optimum number of repeaters to insert in the bus lines. Our derived expressions yield to bus implementations with significant lower cost in terms of area overhead and power consumption than alternative solutions in literature. Considering a 32 nm technology as a significant example, we show that, compared to the traditional solution that inserts repeaters implemented as a single inverter, our strategy enables reductions up to 84% in terms of area overhead, up to 65% in power consumption, and up to 66% in power-delay product. Compared to three recent alternative solutions in the literature, our strategy enables reductions up to 88% in terms of area overhead, up to 48% in power consumption, and up to 43% in power-delay product. Therefore, our approach is particularly suitable to the growing market of mobile applications that require low cost in terms of power consumption and chip area
Impact of Soft Errors on High Performance Autoencoders for Cyberattack Detection
Full text linkDetecting anomalous messages generated by
cyberattacks is essential for IoT based critical applications (e.g.,
finance, healthcare, manufacturing, etc.), in order to guarantee
high levels of security and availability. Autoencoder-based
anomaly detection has been proven effective in detecting the
presence of messages altered by malicious attacks. To guarantee
low detection latency, autoencoders’ algorithms are typically
executed by HW accelerators implemented by nanotechnology.
However, such HW accelerators are susceptible to soft errors
(SEs), that may occur during their in-field operation. In this
paper, we analyze the impact of SEs on the effectiveness of
autoencoders in detecting anomalous messages generated by
cyberattacks. As an example, we consider autoencoders trained
to discriminate credit card legal and illegal transactions. We
show that SEs do not decrease system’s security, but may reduce
system’s availability of the 70%, so that proper solutions to
avoid the detrimental impact of SEs on system’s availability
should be devised for autoencoders implemented by high
performance HW accelerators
Self-checking monitor for NBTI due degradation
Full text linkPerformance degradation of integrated circuits due to aging effects, such as Negative Bias Temperature Instability (NBTI), is becoming of great concern for current and future CMOS technology. In this paper we propose a monitor able to detect NBTI due late transitions in the combinational part of a critical data-path. It requires lower area than recently proposed alternative solutions, and a lower or comparable power consumption. Moreover, differently from alternative solutions, our monitor is also self-checking with respect to its possible internal faults, thus avoiding the useless negative impact on system performance and the negative impact on system reliability which could otherwise take place in case of non self-checking sensors, should they get affected by faults
- …
