1,721,014 research outputs found
Improved sub-threshold slope in short channel vertical MOSFETs using FILOX oxidation
Full text linkThis paper investigates the origins of sub-threshold slope degradation in vertical MOSFETs (v-MOSFETs) due to dry etching of the polysilicon surround gate. Control v-MOSFETs exhibit a degradation of sub-threshold slope as the channel length is reduced from 250 to 100 nm, with 100 nm transistors having a value of 125 mV/dec and a DIBL of 210 mV/V. The effect of the polysilicon gate etch is investigated using a frame-gate architecture in which the polysilicon gate overlaps the side of the pillar, thereby protecting the channel from etch damage. This device shows no degradation of short channel effects when the channel length is scaled and exhibits a near-ideal sub-threshold slope of 76 mV/dec and a DIBL of 33 mV/V at a channel length of 100 nm. Gated diode measurements unambiguously demonstrate that this improved sub-threshold slope is due to the elimination of etch damage at the top and bottom of the pillar created during polysilicon gate etch. An alternative method of eliminating dry etch damage is then investigated by optimizing the Fillet Local Oxidation (FILOX). These devices give a sub-threshold slope of 81 mV/dec and a DIBL of 25 mV/V at a channel length of 100 nm. The improved immunity to dry etch damage is due to the creation of a thick protective oxide at the top and bottom of the pillar during the FILOX proces
Review of SiGe HBTs on SOI
No full textThis paper reviews progress in SiGe Heterojunction Bipolar Transistors (HBT) on Silicon-On-Insulator (SOI) technology. SiGe HBTs on SOI are attractive for mixed signal radio frequency (RF) applications and have been of increasing research interest due to their compatibility with SOI CMOS (Complementary Metal Oxide Semiconductor) technology. In bipolar technology, the use of SOI substrate eliminates parasitic substrate transistors and associated latch-up, and has the ability to reduce crosstalk, particularly when combined with buried groundplanes (GP). Various technological SOI bipolar concepts are reviewed with special emphasis on the state-of-the-art SOI SiGe HBT devices in vertical and lateral design. More in depth results are shown from a UK consortium advanced RF platform technology, which includes SOI SiGe HBTs. Bonded wafer technology was developed to allow incorporation of buried silicide layers both above and below the buried oxide. New electrical and noise characterisation results pointed to reduced 1/f noise in these devices compared to bulk counterparts. The lower noise is purported to arise from strain relief of the device structure due to the elasticity of the buried oxide layer during the high temperature epitaxial layer growth. The novel concept of the silicide SOI (SSOI) SiGe HBT technology developed for targeting a reduction in collector resistance, as well as for suppressing the crosstalk, is outlined. The buried tungsten silicide layers were found to have negligible impact on junction leakage. Further to vertical SiGe HBTs on SOI, the challenges of fabricating a lateral SOI SiGe HBT structure are presented
A Technology for Building Shallow Junction MOSFETs on Vertical Pillar Walls
No full textThis work addresses a fundamental problem of vertical MOSFETS, that is, inherently deep junctions that exacerbate short channel effects (SCE). A self-aligned oxide region, or junction stop (JS) is formed at the top of the pillar and the shallow drain junction is then formed by out-diffusion from an overlying poly-crystalline drain contact region. The efficacy of the approach is demonstrated by simulation and the influence of the JS on SCE clearly shown. The process has been used to produce experimental devices that are characterized and discussed in the context of the modeling
Current crowding effects in SOI-SiGe HBTs with low doped emitters
No full textAnomalous limitation of collector and base current in SOI SiGe HBTs at moderate bias levels is shown to be the result of current crowding and associated high injection effects induced by emitter de-biasing in the low doped emitter rather than in the base as is the case for homojunction transistors. Experimental results from devices with decreasing emitter window dimension, re-enforced by 2-D simulation, show clearly a trend for crowding at the centre as the emitter resistance increases. The results have significance for achieving full optimisation of HBTs and in particular, for medium power devices
Non-selective growth of SiGe heterojunction bipolar transistor layers at 700C with dual control of n and p type dopant profiles
No full textThis paper describes the growth of the collector, base and emitter layers of a SiGe HBT in a single epitaxy process. A non-selective SiGe heterojunction bipolar transistor growth process at 700C has been developed, which combines n-type doping for the Si collector, p-type doping for the SiGe base and n-type doping for the Si emitter cap. Control of the collector doping concentration by varying the growth conditions is shown. The boron tailing edge from the SiGe base into the Si emitter layer was removed by interrupting the growth process with a hydrogen flow after the SiGe base growth but before the Si emitter growth to remove the dopant gas from the chamber. The layer thicknesses are compared using three different analytical techniques: SIMS, TEM and spectro-ellipsometry. A good agreement was obtained for the three different methods
The influence of junction depth on short channel effects in vertical sidewall MOSFETs
No full textThis work addresses a fundamental problem of vertical MOSFETs, that is, inherently deep junctions that exacerbate short channel effects (SCEs). Due to the unconventional asymmetric junction depths in vertical MOSFETs, it is necessary to look separately at the electrostatic influence of each junction. In order to suppress short channel effects better, we explore the formation of a shallow drain junction. This is realized by a self-aligned oxide region, or junction stop US) which is formed at the pillar top and acts as a diffusion barrier for shallow junction formation. The benefits of using a JS structure in vertical MOSFETs are demonstrated by simulations which show clearly the effect of asymmetric junctions on SCEs and bulk punch-through. A critical point is identified, where control of SCEs by junction depth is lost and this leads to appropriate junction design in JS vertical sidewall MOSFETs. For a 70 nm channel length the JS structure improves charge sharing by 54 mV and DIBL by 46 mV. For body dopings of 5.0 x 1017 cm-3 and 6.0 x 1017 cm-3 the JS gives improvements in I-off of 58.7% and 37.8%, respectively, for a given I-on. The inclusion of a retrograde channel gives a further increase in I-on of 586 µA/µm for a body doping of 4.0 x 1018 cm-3
SiGeC HBTs: impact of carbon on performance
No full textA UK consortium has recently reported advanced RF platform technology, which includes SiGe Heterojunction Bipolar Transistors (HBT) on Silicon-On-Insulator (SOI). The study in this paper is the continuation of consortium work, focused on fabricating SiGeC HBTs and on impact of C (up to 1.6%) on device performance. The devices with low C content (0.45%) exhibit excellent performance and gain up to 500. The results indicate that C content to be used in these devices should be less than 1%
Shallow junctions on pillar sidewalls for sub-100-nm vertical MOSFETs
No full textA simple process is described for the fabrication of a shallow drain junction on a pillar sidewall in sub-100nm vertical MOSFETs. The key feature of this process is the creation of a polysilicon spacer around the perimeter of the pillar to connect the channel to a polysilicon drain contact. The depth of the junction on the pillar sidewall is primarily determined by the thickness of the polysilicon spacer. This process is CMOS compatible, and hence facilitates the integration of a sub-100nm vertical MOSFET in a planar CMOS technology using mature lithography. The fabricated transistors have a sub-threshold slope of 95mV/dec (at VDS =1V) and a DIBL of 0.12V
Series resistance in vertical MOSFETs with reduced drain/source overlap capacitance
No full textIn this work we investigate the series resistances in vertical MOSFETs incorporating the fillet local oxidation (FILOX) structure that serves to reduce the gate to drain/source overlap capacitances. The series resistances are modeled analytically and the important influencing factors, namely gate bias dependence and the asymmetric nature of the device, are identified. We extract by simulation, Rd and Rs from devices with different FILOX thicknesses, employing an impedance method often used in RF characterisation. We identify the trade-off whereby thickening the FILOX first causes an increase of the cut-off frequency fT, until the on-current Ion becomes limited by increasing series resistances and fT therefore reduces. The results indicate a thickness of 40nm FILOX for maximum fT. We also investigate the influence of process conditions on low series resistances, namely time of rapid thermal annealing RTA and angle of implantation
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