12,859 research outputs found
Buffer Block Planning for Interconnect-Driven Floorplanning
No full textThis paper studies buffer block planning for interconnect-driven floorplanning in deep submicron designs. We first introduce the concept of feasible region (FR) for buffer insertion, and derive closed-form formula for FR. We observe that the FR for a buffer is quite large in general even under fairly tight delay constraint. Therefore, FR gives us a lot of flexibility to plan for buffer locations. We then develop an effective buffer block planning (BBP) algorithm to perform buffer clustering such that the overall chip area and the buffer block number can be minimized. To the best of our knowledge, this is the first in-depth study on buffer planning for interconnect-driven floorplanning with both area and delay consideration
Buffer block planning for interconnect-driven floorplanning
No full textThis paper studies buffer block planning for interconnect-driven floorplanning in deep submicron designs. We first introduce the concept of feasible region (FR) for buffer insertion, and derive closed-form formula for FR. We observe that the FR for a buffer is quite large in general even under fairly tight delay constraint. Therefore, FR gives us a lot of flexibility to plan for buffer loca-tions. We then develop an effective buffer block planning (BBP) algorithm to perform buffer clustering such that the overall chip area and the buffer block number can be minimized. To the best of our knowledge, this is the first in-depth study on buffer planning for interconnect-driven floorplanning with both area and delay consid-eration.
Mitigating Receiver’s Buffer Blocking by Delay Aware Packet Scheduling in Multipath Data Transfer
Get PDFReliable in-order multi-path data transfer under asymmetric heterogeneous network conditions has known problems related to receiver's buffer blocking, caused by out of order packet arrival. Consequently, the aggregate capacity from multiple paths, which theoretically should be available to and achievable by the multi-path transport protocol, is practically severely underutilized. Several mitigation techniques have been proposed to address this issue mostly by using various packet retransmission schemes, load-balancing and bandwidth-estimation based mechanisms.
In comparison to the existing reactive techniques for buffer block mitigation, we propose a novel and yet simpler to implement, delay aware packet scheduling scheme for multipath data transfer over asymmetric network paths, that proactively minimizes the blocking inside receiver's buffer.
Our initial simulation results show that, in comparison to the default round robin packet scheduler, by using our proposed delay aware packet scheduling scheme, we can significantly improve the overall performance of a multi-path transport protocols while notably minimizing the receiver's buffer usage. Therefore, our proposal is particularly beneficial for multi-homed hand-held mobile devices with limited buffering capacity, which, due to their multi-homing and heterogeneous wireless network features (i.e. availability of 3G and Wi-Fi) are also one of the most common use cases for multi-path transport
Consumer Demand and Welfare under Increasing Block Pricing
Get PDFThis paper argues that an increasing block pricing structure needs to be supplemented by allowances for household size and composition to be equitable. Household behaviour is modelled as the outcome of a two-stage budgeting resulting in an integrable water demand model. The welfare effects of block pricing are studied using the concept of relative equivalence scale, modified to allow for the dependence of price on household size and composition. We use individual household data to estimate residential demand for water, provide empirical illustration of the welfare effects of increasing block pricing on demographically different households and show how these effects can be compensated.relative equivalence scales, price endogeneity, demand for water
Provably Good Global Buffering Using an Available Buffer Block Plan
No full textTo implement high-performance global interconnect without impacting the performance of existing blocks, the use of buffer blocks is increasingly popular in structured-custom and block-based ASIC/SOC methodologies. Recent works by Cong et al. [6] and Tang and Wong [25] give algorithms to solve the buffer block planning problem. In this paper we address the problem of how to perform buffering of global nets given an existing buffer block plan. Assuming as in [6, 25] that global nets have been already decomposed into two-pin connections, we give a provably good algorithm based on a recent approach of Garg and Konemann [8] and Fleischer [7]. Our method routes connections using available buffer blocks, such that required upper and lower bounds on buffer intervals -- as well as wirelength upper bounds per connection -- are satisfied. Unlike [6, 25], our model allows more than one buffer to be inserted into any given connection. In addition, our algorithm observes buffer parity constraints, i.e., it will choose to use an inverter or a buffer (= co-located pair of inverters) according to source and destination signal parity. The algorithm outperforms previous approaches [6] and has been validated on top-level layouts extracted from a recent high-end microprocessor design
Resist Free Patterning of Nonpreferential Buffer Layers for Block Copolymer Lithography
No full textWe report the design of a direct electron beam patternable buffer layer to spatially control the orientation of the microdomains in an overlaying polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) block copolymer (BCP) film. The buffer layer consists of a surface anchored low molecular weight PS-b-PMMA, with the PMMA segment anchored to the surface and a short PS block at the buffer layer/BCP interface. The block architecture of the buffer layer combines the essential features of “bottom up” and “top down” approaches as it functions as a nonpreferential layer to dictate perpendicular orientation of BCP domains from the substrate interface and as an e-beam resist to allow top-down lithographic process to spatially define the buffer layer on the substrate. The composition of the buffer layer can be tuned by changing the relative block lengths to create a nonpreferential surface which effectively induces perpendicular orientation of domains in an overlying BCP film. The grafted block copolymer can be locally shaved by e-beam lithography resulting in spatial control of domain orientation in the BCP film. The direct patterning approach reduces the number of steps involved in forming chemical patterns by conventional lithography
Characterization of Block Reference Pattern for Flexible and Adaptive Buffer Management Scheme
No full textTo overcome the speed gap between processors and disks, many computer systems utilize buffer cache located in main memory. Previous works on buffer cache management mainly use a single fixed block replacement policy such as LRU policy. However, block reference patterns of applications vary depending on the nature of applications, which requires applying different replacement policies to different applications. In this paper, we propose a new adaptive buffer management scheme. Our approach is based on the automatic detection of block reference patterns of applications. The detection is made by associating block attributes such as backward distance and frequency with forward distance of a block. The scheme can classifies four reference patterns: sequential, looping, temporally-clustered, and probabilistic. According to the detected patterns, the scheme applies an appropriate block replacement policy to each application. Also, the scheme employs an efficient block allocation strategy to m..
Assessing Moving Block Railway Capacity Based on Fixed Block Infrastructure Occupation
No full textMoving block signalling promises a significant reduction of the infrastructure occupation compared to a fixed block system, such as NS’54/ATB. This is mainly caused by a strong reduction of the approach and running time. However, to assess the capacity gains track occupation data, such as blocking times are needed. ETCS L3 Moving Block is still in development, so gathering data out of daily operations is not possible. Also gathering moving block data out of simulation isn’t always a convenient solution. For example, in simulation software FRISO, used at ProRail, ETCS L3 Moving Block is not (yet) implemented. With infrastructure data, rolling stock parameters and planned time-distance data, blocking times for a moving block signalling system can be estimated. The model presented in this thesis has an average error of 0.87s to the blocking time. In 95% of the cases the error is within a range of (-3,3) seconds. Given that ProRail plans with a precision of 6 seconds, it can be concluded that the model both precise as accurate. With the blocking times of all trains, bottlenecks in both railway corridors and complex nodes can be identified. One could sum all blocking times per block and consider blocks with the highest summed blocking times as bottleneck. However, this can only be applied for homogeneous traffic situations. Another approach is identifying bottlenecks by the shortest buffer time between two trains, also called a critical block. This can be applied for both homogeneous as heterogeneous traffic situations. An advantage is that it is not needed to split corridors into line sections. One could analyse a whole network at once and identify bottleneck at a microscopic level. By keeping the same timetable, the buffer time between two trains increases on average by 75 seconds (60%) using moving block over NS’54.Civil Engineering | Transport and Plannin
Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations
No full textAbstract During the routing of global interconnects, macro blocks form useful routing regions which allow wires to go through but forbid buffers to be inserted. They give restrictions on buffer locations. In this paper, we take these buffer location restrictions into consideration and solve the simultaneous maze routing and buffer insertion problem. Given a block placement defining buffer location restrictions and a pair of pins (a source and a sink), we give a polynomial time exact algorithm to find a buffered route from the source to the sink with minimum Elmore delay. 1 Introduction With the evolution of VLSI fabrication technology, interconnect delay, especially global interconnect delay, has become the dominant factor in deep sub-micron design. Many techniques are employed to reduce interconnect delay; among them, buffer insertion has been shown to be an effective approach [2]. During routing process, especially that for global nets, there are macro blocks placed within the area. These blocks form useful routing regions because wires are allowed to run over them. But since buffers are implemented by transistors, a buffer "over " a macro block must be actually put into that block. However, it is impossible to insert a buffer into a macro block if it is an IP (Intellectual Property) where internal structure can not be changed, or it is a block such as memory which requires regular layout. Even in the case when that is theoretically possible, since a re-design of the influenced block is needed, it is usually not allowed due to the design flow. Therefore, macro blocks present themselves as routing resources for wires but obstacles for buffers
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