4,141 research outputs found
Making acceleration more amenable with novel high-level synthesis techniques for FPGAs
No full textL'abstract è presente nell'allegato / the abstract is in the attachmen
A DSP shared is a DSP earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs
No full textHigh-level synthesis (HLS) enhances digital hardware design productivity through a high abstraction level. Even if the HLS abstraction prevents fine-grained manual register-transfer level (RTL) optimizations, it also enables automatable optimizations that would be unfeasible or hard to automate at RTL.
Specifically, we propose a task-level multi-pumping methodology to reduce resource utilization, particularly digital signal processors (DSPs), while preserving the throughput of HLS kernels modeled as dataflow graphs (DFGs) targeting field-programmable gate arrays. The methodology exploits the HLS resource sharing to automatically insert the logic for reusing the same functional unit for different operations. In addition, it relies on multi-clock DFGs to run the multi-pumped tasks at higher frequencies.
The methodology scales the pipeline initiation interval (II) and the clock frequency constraints of resource-intensive tasks by a multi-pumping factor (M). The looser II allows sharing the same resource among M different operations, while
the tighter clock frequency preserves the throughput. We verified that our methodology opens a new Pareto front in the throughput and resource space by applying it to open-source HLS designs using state-of-the-art commercial HLS and implementation tools by Xilinx. The multi-pumped designs require up to 40% fewer DSP resources at the same throughput as the original designs optimized for performance (i.e., running at the maximum clock frequency) and achieve up to 50% better throughput using the same DSPs as the original designs optimized for resources with a single clock
To Spike or Not To Spike: A Digital Hardware Perspective on Deep Learning Acceleration
No full textAs deep learning models scale, they become increasingly competitive from domains spanning from computer vision to natural language processing; however, this happens at the expense of efficiency since they require increasingly more memory and computing power. The power efficiency of the biological brain outperforms any large-scale deep learning (DL) model; thus, neuromorphic computing tries to mimic the brain operations, such as spike-based information processing, to improve the efficiency of DL models. Despite the benefits of the brain, such as efficient information transmission, dense neuronal interconnects, and the co-location of computation and memory, the available biological substrate has severely constrained the evolution of biological brains. Electronic hardware does not have the same constraints; therefore, while modeling spiking neural networks (SNNs) might uncover one piece of the puzzle, the design of efficient hardware backends for SNNs needs further investigation, potentially taking inspiration from the available work done on the artificial neural networks (ANNs) side. As such, when is it wise to look at the brain while designing new hardware, and when should it be ignored? To answer this question, we quantitatively compare the digital hardware acceleration techniques and platforms of ANNs and SNNs. As a result, we provide the following insights: (i) ANNs currently process static data more efficiently, (ii) applications targeting data produced by neuromorphic sensors, such as event-based cameras and silicon cochleas, need more investigation since the behavior of these sensors might naturally fit the SNN paradigm, and (iii) hybrid approaches combining SNNs and ANNs might lead to the best solutions and should be investigated further at the hardware level, accounting for both efficiency and loss optimization
Le «buone letture». 2. Giovanni Casati
No full textIl saggio è costituito da due parti, la prima delle quali, dedicata alla fondazione della Federazione italiana delle biblioteche circolanti cattoliche, è stata pubblicata nel precedente numero dei «Nuovi Annali», XXVII (2013), pp. 137-163. In questa seconda parte viene delineata la figura intellettuale di Giovanni Casati, che diresse la «Rivista di letture» dal 1912 al 1944, trasformando il periodico della Federazione in una rivista impegnata nella divulgazione della cultura cattolica. A questo impegno militante Casati fece corrispondere un intenso programma editoriale, che trovò espressione nella pubblicazione di saggi letterari, di manuali e opere repertoriali.The study consists of two parts; the first is dedicated to the history of the Federazione italiana delle biblioteche circolanti cattoliche since its foundation (1904) up to 1912 and was published in the previous volume of the «Nuovi Annali », XXVII (2013), pp. 137-163. In this second part, the author outlines the intellectual figure of Giovanni Casati, who directed the «Rivista di letture» from 1912 to 1944, transforming the magazine of the Federation in a journal engaged in the spreading of Catholic culture. To this militant engagement Casati matched an intense publishing program, which found its expression in the publication of literary essays, manuals and reference works
An inverse scattering based hybrid method for the measurement of the complex dielectric permittivities of arbitrarily shaped homogenous targets
No full textIn this paper we present a hybrid approach for the measurement of the complex dielectric permittivities of arbitrarily shaped homogeneous dielectric scatterers by using microwaves. The proposed method is organized in two stages: in the first one, the supports of the scatterers are retrieved by means of a new formulation of the linear sampling method, which is based on the no sampling approach; in the second one, the complex permittivities of the targets are estimated by means of a quantitative method, which searches the solution within the constraints provided by the previous step. In such a way, the efficiency of the new version of the linear sampling method is combined with the accuracy of quantitative procedures. The proposed methodology is assessed against noisy synthetic data, by using the ant colony optimization algorithm as a tool to estimate the dielectric parameters of the inspected targets
A fast and efficient microwave method for detecting dielectric and conducting bodies inside complex structures
No full textThis contribution presents a fast and efficient method for the inspection of dielectric and conducting bodies located inside arbitrary structures by using microwaves. The presented procedure is able to retrieve both the dielectric permittivity and electric conductivity of arbitrarily shaped targets embedded in inhomogeneous backgrounds and so it is an useful tool for diagnostics in several scenarios. The applications which can mostly benefit from it are non-destructive testing and evaluation of products and the imaging of objects hidden in bags or suitcases
SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators
No full textHigh-level synthesis (HLS) aims at democratizing custom hardware acceleration with highly abstracted software-like descriptions. However, efficient accelerators still require substantial low-level hardware optimizations, defeating the HLS intent. In the context of field-programmable gate arrays, digital signal processors (DSPs) are a crucial resource that typically requires a significant optimization effort for its efficient utilization, especially when used for sub-word vectorization. This work proposes SILVIA, an open-source LLVM transformation pass that automatically identifies superword-level parallelism within an HLS design and exploits it by packing multiple operations, such as additions, multiplications, and multiply-and-adds, into a single DSP. SILVIA is integrated in the flow of the commercial AMD Vitis HLS tool and proves its effectiveness by packing multiple operations on the DSPs without any manual source-code modifications on several diverse state-of-the-art HLS designs such as convolutional neural networks and basic linear algebra subprograms accelerators, reducing the DSP utilization for additions by 70 % and for multiplications and multiply-and-adds by 50 % on average
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