1,721,058 research outputs found
Experimental Study on the Short-Circuit Instability of Cascode GaN HEMTs
No full textThis article presents an experimental investigation on the short-circuit (SC) instability of several commercially available cascode gallium nitride (GaN) high-electron-mobility transistors (HEMTs). In the SC test, self-sustained oscillation is observed during the SC transient. The SC oscillation features some unique characteristics. The gate resistor shows very weak damping effect on the SC oscillation. The SC oscillation thereby cannot be suppressed by utilizing a large gate resistor. With the increase in the dc-bus voltage, the SC oscillation greatly amplifies and becomes more unstable. When the dc-bus voltage reaches 200-250 V, catastrophic failure occurs. In the SC test, two distinct failure modes, which are related to the failure of low-voltage (LV) MOSFET and depletion-mode HEMTs (DHEMTs), are identified. Based on the experimental evidence and simulation study, the root causes of the failure are clarified in the end
Self-sustained Oscillation of Superjunction MOSFET Intrinsic Diode during Reverse Recovery Transient
No full textInvestigation on the Short-Circuit Oscillation of Cascode GaN HEMTs
No full textThis article presents the study on the self-sustained oscillation of cascode gallium nitride (GaN) high-electron-mobility transistors (HEMTs), which occurs under the short-circuit (SC) condition. Based on the SC test, it is found that the self-sustained oscillation can be excited in the SC event of cascode GaN HEMTs. Moreover, the gate resistance R {G} does not have a significant damping effect on the self-sustained SC oscillation. The SPICE simulation is performed to study the oscillation waveforms of the internal depletion-mode HEMT (DHEMT) and low-voltage (LV) mosfet. This article reveals two positive feedback loops, which excite the SC oscillation. One loop is related to the positive feedback process of the DHEMT itself. Another loop is induced by the interaction between the DHEMT and LV mosfet. The two positive feedback loops are interrelated and can reinforce each other. As a result, a very strong driving force is generated to excite the self-sustained oscillation. During the oscillatory transient, the parasitic elements of the device's package play a critical role in exciting the positive feedback process. By analyzing the influence of the parasitic elements on the positive feedback process, the necessary methods are proposed to suppress the SC oscillation. The SPICE simulation validates the effectiveness of the proposed methods
Self-sustained turn-off oscillation of SiC MOSFETs: Origin, instability analysis, and prevention
No full textAbstract: This paper presents a comprehensive investigation on the self-sustained oscillation of silicon carbide (SiC) MOSFETs. At first, based on the double pulse switching test, it is identified that the self-sustained oscillation of SiC MOSFETs can be triggered by two distinct test conditions. To investigate the oscillatory criteria of the two types of self-sustained oscillation, a small-signal ac model is introduced to obtain the transfer function of the oscillatory system. The instability of the oscillation is thereby determined by the two conjugate pole pairs of the transfer function. By analyzing the damping ratios of the two pole pairs, the parametric sensitivity of various circuit and device’s parameters on the two types of self-sustained oscillation are obtained. The analyses reveal the oscillatory criteria of the self-sustained oscillation for SiC MOSFETs. Based on the oscillatory criteria, necessary methods are proposed to prevent the oscillation. The proposed oscillation suppression methods are validated by the experiment at the end of the paper
A Comprehensive Investigation on Short-Circuit Oscillation of p-GaN HEMTs
No full textThis article presents a study on the short-circuit (SC) instability of p-doped gate gallium nitride (p-GaN) high-electron-mobility transistors (HEMTs). Under SC condition, self-sustained oscillation occurs when a package stray inductance is introduced in a common source. The SC oscillation features some unique characteristics. With higher dc-bus voltage, the SC oscillation tends to be more unstable. The SC oscillation of p-GaN HEMTs is, thereby, a real threat to the converter operation. When the common-source inductance is eliminated or a larger gate resistor is utilized, the SC oscillation can be dampened. Due to the SPICE simulation, the self-sustained SC oscillation is reproduced. The analyses on the simulated waveforms reveal a positive feedback mechanism that excites the SC oscillation. An analytical model is, thereby, derived to analyze the instability of the positive feedback system. The analyses reveal that the SC oscillation becomes more unstable when the power loop or gate loop has smaller stray inductances, which makes some conventional oscillation suppression methods invalid. To avoid SC oscillation, some effective guidelines are proposed at the end of the article
Atrial Fibrillation Detection by Means of Edge Computing on Wearable Device: A Feasibility Assessment
No full textCardio Vascular Diseases (CVDs) represent one of the main burden that affected world population in the last and in the current decades. The early detection by means of wide screening population-wide may represent a good path to avoid the worsening of pre-existent situation. In this arena, the use of wearable devices in combination with deep learning to deliver edge computing system seems to be the most viable pathway to follow in order to fight the CVDs burden. Despite the fact that many studies have concentrated on edge computing techniques for CVDs, there is a limited literature on Atrial Fibrillation (AF) detection directly on-device. Due to limited availability of research on this topic, the feasibility assessment of an on-device edge computing wearable system is described in this work. Starting with an examination of the features to be considered, the study progresses through the building of a Neural Network (NN), the training of the model, and the on-cloud testing process to completion. The NN is composed of 4 hidden layer made up of respectively 5, 30, 20 and 10 node. The learning rate is 0.005 and the number of training cycle is 30. The training set consists of 3362 windows, and the testing set consists of 796 windows. The findings of the test are encouraging, with an output F1-score of 0.94 for AF recognition as a result of the test. The model is then deployed on-device and evaluated offline, without the need for any additional devices or an internet connection, in order to run the inference process. Finally, the system that will be used for future human trials is presented, together with a description of the factors that led to the selection of this particular system and the major characteristic of the sensors
Total Area Current Distribution Analysis during UIS Test for 600 v Power Diode by Lock-In Thermography
No full textThe power semiconductor devices market is pushing for the development of power diodes with a superior robustness in avalanche conditions. This requirement becomes crucial in those applications where the load is an inductance. Therefore, the unclamped inductive switching (UIS) test is commonly adopted for the validation of a new design. When the device under test (DUT) exhibits a reduced avalanche capability, the lock-in thermography (LIT) is a powerful characterization tool for the analysis of the current distribution over the whole device during the UIS test. In this work, the current distribution over the whole area of a 600 V Power Diode during the UIS is investigated by means of the LIT. A complex current distribution dynamics before the device failure arises from the LIT measurements and the experimental temperature maps are here presented
Gate Driver for p-GaN HEMTs with Real-Time Monitoring Capability of Channel Temperature
No full textNormally-off p-GaN HEMTs with Schottky-type gate are becoming of common adoption in both industrial and consumer electronic market. The presence of a gate current with a remarkable dependence on the temperature of the device allows embedding a temperature sensing feature with very fast response into the gate-driving circuitry. In this work, a prototype of a gate driver circuit with temperature monitoring capability is presented and its applicability in a broad range of operating conditions is validated by means of a thorough experimental campaign
An Electrothermal Compact Model for SiC MOSFETs Based on SPICE Primitives with Improved Description of the JFET Resistance
No full textThis manuscript introduces a compact electrothermal model for SiC power MOSFETs that can be easily scaled to devices of different voltage ratings. The model is implemented as a subcircuit containing mainly SPICE native components. Both the static and dynamic performance can be tuned by adjusting a small set of parameters. The model is validated on 1.7 kV-60 A-rated devices
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