1,535,168 research outputs found
Space-time decision feedback equalisation using a minimum bit error rate design for single-input multi-output channels
No full textThis contribution proposes a minimum bit error rate (MBER) decision feedback equaliser (DFE) designed for single-input multiple-output (SIMO) systems employing a quadrature phase shift keying (QPSK) modulation scheme. It is shown that this MBER design is superior over the standard minimum mean square error DFE in the SIMO scenario considered, in terms of the achievable system bit error rate. A sample-by-sample adaptive implementation of this MBER DFE is derived, which is referred to as the least bit error rate (LBER) algorithm. It is shown that for SIMO systems using a QPSK scheme, the LBER algorithm has a similar computational complexity as the simple least mean square (LMS) algorithm. Simulation results demonstrate that the proposed adaptive LBER-based DFE outperforms the adaptive LMS-based DFE, in both stationary and fading cases. Index Terms: Single-input multiple-output, multiple antennas, space-time processing, decision feedback equaliser, minimum mean square error, minimum bit error rat
Bit-level pipelined digit-serial array processors
No full textA new architecture for high performance digit-serial vector inner product (VIP) which can be pipelined to the bit-level is introduced. The design of the digit-serial vector inner product is based on a new systematic design methodology using radix-2n arithmetic. The proposed architecture allows a high level of bit-level pipelining to increase the throughput rate with minimum initial delay and minimum area. This will give designers greater flexibility in finding the best tradeoff between hardware cost and throughput rate. It is shown that sub-digit pipelined digit-serial structure can achieve a higher throughput rate with much less area consumption than an equivalent bit-parallel structure. A twin-pipe architecture to double the throughput rate of digit-serial multipliers and consequently that of the digit-serial vector inner product is also presented. The effect of the number of pipelining levels and the twin-pipe architecture on the throughput rate and hardware cost are discussed. A two's complement digit-serial architecture which can operate on both negative and positive numbers is also presented
Two research contributions in 64-bit computing: Testing and Applications
No full textFollowing the release of Windows 64-bit and Redhat Linux 64-bit operating systems (OS) in late April 2005, this is the one of the first 64-bit OS research project completed in a British university. The objective is to investigate (1) the increase/decrease in performance compared to 32-bit computing; (2) the techniques used to develop 64-bit applications; and (3) how 64-bit computing should be used in IT and research organizations to improve their work. This paper summarizes research discoveries for this investigation, including two major research contributions in (1) testing and (2) application development. The first contribution includes performance, stress, application, multiplatform, JDK and compatibility testing for AMD and Intel models. Comprehensive testing results reveal that 64-bit computing has a better performance in application performance, system performance and stress testing, but a worse performance in compatibility testing than the traditional 32-bit computing. A 64-bit dual-core processor has been tested and the results show that it performs better than a 64-bit single-core processor, but only in application that requires very high demands of CPU and memory consumption. The second contribution is .NET 1.1 64-bit implementations. Without additional troubleshooting, .NET 1.1 does not work on 64-bit Windows operating systems in stable ways. After stabilizing .NET environment, the next step is the application development, which is a dynamic repository with functions such as registration, download, login-logout, product submissions, database storage and statistical reports. The technology is based on Visual Studio .NET 2003, .NET 1.1 Framework with Service Pack 1, SQL Server 2000 with Service Pack 4 and IIS Server 6.0 on the Windows Server 2003 Enterprise x64 platform with Service Pack 1
Model based optimal bit allocation
Get PDFModeling of the operational rate-distortion characteristics of a signal can significantly reduce the computational complexity of an optimal bit allocation algorithm. In this report, such models are studied
Minimum bit-error rate design for space-time equalization-based multiuser detection
No full textA novel minimum bit-error rate (MBER) space–time equalization (STE)-based multiuser detector (MUD) is proposed for multiple-receive-antenna-assisted space-division multiple-access systems. It is shown that the MBER-STE-aided MUD significantly outperforms the standard minimum mean-square error design in terms of the achievable bit-error rate (BER). Adaptive implementations of the MBER STE are considered, and both the block-data-based and sample-by-sample adaptive MBER algorithms are proposed. The latter, referred to as the least BER (LBER) algorithm, is compared with the most popular adaptive algorithm, known as the least mean square (LMS) algorithm. It is shown that in case of binary phase-shift keying, the computational complexity of the LBER-STE is about half of that required by the classic LMS-STE. Simulation results demonstrate that the LBER algorithm performs consistently better than the classic LMS algorithm, both in terms of its convergence speed and steady-state BER performance. Index Terms—Adaptive algorithm, minimum bit-error rate (MBER), multiuser detection (MUD), space–time processing
Near-Capacity Irregular Bit-Interleaved Coded Modulation
Get PDFAn Irregular Bit-Interleaved Coded Modulation based Iterative Decoding (Ir-BICM-ID) aided scheme is proposed. The irregularity of the scheme pervades the three basic components of BICM-ID, namely the encoder, the unity-rate precoder and the bit-to-symbol mapper. As a result, adaptive BICM-ID schemes constituted by irregular components are created, which are capable of approaching the capacity of coded modulation. This is achieved by creating a narrow EXtrinsic Information Transfer (EXIT) chart, using a novel EXIT curve matching algorithm. The proposed Ir-BICM-ID scheme employs Irregular Convolutional Codes (IrCC), Irregular Unity-Rate Codes (IrURC) and Irregular Mappers (IrMapper)
Low latency low power bit flipping algorithms for LDPC decoding
Get PDFLow Density Parity Check (LDPC) codes have been adopted in a number of wired and wireless communication standards due to their improved error correcting ability and relatively simple decoder structure. However, for very high throughput systems operating in the multi-Gb/s range conventional decoding methods based on message passing are limited, due largely to the sheer volume of messages being exchanged. Thus, simpler decoding methods have been proposed such as bit flipping permitting efficient and fast hardware implementation. This paper presents two new bit flipping algorithm designed to reduce latency and power consumption. For a small loss in bit error rate performance (0.5 dB) we show how the application of an early stopping criteria uses 89% fewer iterations compared to a similar published algorithm. We also present a method for reducing power consumption by placing processing elements into a quiescent state based on a bit-local metric. Using this technique we show a potential reduction in power consumption of 76%.Low Density Parity Check (LDPC) codes have been adopted in a number of wired and wireless communication standards due to their improved error correcting ability and relatively simple decoder structure. However, for very high throughput systems operating in the multi-Gb/s range conventional decoding methods based on message passing are limited, due largely to the sheer volume of messages being exchanged. Thus, simpler decoding methods have been proposed such as bit flipping permitting efficient and fast hardware implementation. This paper presents two new bit flipping algorithm designed to reduce latency and power consumption. For a small loss in bit error rate performance (0.5 dB) we show how the application of an early stopping criteria uses 89% fewer iterations compared to a similar published algorithm. We also present a method for reducing power consumption by placing processing elements into a quiescent state based on a bit-local metric. Using this technique we show a potential reduction in power consumption of 76%
Adaptive Minimum Bit Error Rate Beamforming Assisted QPSK Receiver
No full textA novel adaptive beamforming technique is proposed for wireless communication with quadrature phase shift keying signalling based on the minimum bit error rate (MBER) criterion. It is shown that the MBER approach provides significant performance gain in terms of smaller bit error rate over the standard minimum mean square error approach. Using the classical Parzen window estimate of probability density function, both the block-data and sample-by-sample adaptive implementations of the MBER solution are developed
Sorting without exchanges on a bit-serial systolic array
No full textThe author considers, a number of bit-serial systolic designs for ordering a list of n elements without 'on-the-fly' exchanges are considered. The algorithms require 4n+p+k bit steps where p=log2 n and k is the number of bits required to encode all the possible elements. The arrays require O(n(p+k)) bit cells with a complexity roughly the same as that of a full adder and between max (p,k) and p+k input/output pins. The input to the array is the list to be sorted and an auxiliary vector whose elements have bit length p. The output is the list itself and the auxiliary vector, which is updated to produce pointers to the correct position of each element in the ordered list
"Cuando se piensa en un solo tipo de usuario se deja afuera a muchos otros" : Entrevista a María del Carmen Malbrán
No full textLa reconocida profesora y experta en temas vinculados a la educación, María del Carmen Malbrán, conversó con Bit&Byte. El diálogo se enmarcó sobre cómo las relaciones humanas son atravesadas por las nuevas tecnologías, generando acercamientos y distancias. También sobre el impacto en el proceso de enseñanza aprendizaje.Facultad de Informátic
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