1,934,639 research outputs found
Two research contributions in 64-bit computing: Testing and Applications
No full textFollowing the release of Windows 64-bit and Redhat Linux 64-bit operating systems (OS) in late April 2005, this is the one of the first 64-bit OS research project completed in a British university. The objective is to investigate (1) the increase/decrease in performance compared to 32-bit computing; (2) the techniques used to develop 64-bit applications; and (3) how 64-bit computing should be used in IT and research organizations to improve their work. This paper summarizes research discoveries for this investigation, including two major research contributions in (1) testing and (2) application development. The first contribution includes performance, stress, application, multiplatform, JDK and compatibility testing for AMD and Intel models. Comprehensive testing results reveal that 64-bit computing has a better performance in application performance, system performance and stress testing, but a worse performance in compatibility testing than the traditional 32-bit computing. A 64-bit dual-core processor has been tested and the results show that it performs better than a 64-bit single-core processor, but only in application that requires very high demands of CPU and memory consumption. The second contribution is .NET 1.1 64-bit implementations. Without additional troubleshooting, .NET 1.1 does not work on 64-bit Windows operating systems in stable ways. After stabilizing .NET environment, the next step is the application development, which is a dynamic repository with functions such as registration, download, login-logout, product submissions, database storage and statistical reports. The technology is based on Visual Studio .NET 2003, .NET 1.1 Framework with Service Pack 1, SQL Server 2000 with Service Pack 4 and IIS Server 6.0 on the Windows Server 2003 Enterprise x64 platform with Service Pack 1
Model based optimal bit allocation
Full text linkModeling of the operational rate-distortion characteristics of a signal can significantly reduce the computational complexity of an optimal bit allocation algorithm. In this report, such models are studied
Near-Capacity Irregular Bit-Interleaved Coded Modulation
Full text linkAn Irregular Bit-Interleaved Coded Modulation based Iterative Decoding (Ir-BICM-ID) aided scheme is proposed. The irregularity of the scheme pervades the three basic components of BICM-ID, namely the encoder, the unity-rate precoder and the bit-to-symbol mapper. As a result, adaptive BICM-ID schemes constituted by irregular components are created, which are capable of approaching the capacity of coded modulation. This is achieved by creating a narrow EXtrinsic Information Transfer (EXIT) chart, using a novel EXIT curve matching algorithm. The proposed Ir-BICM-ID scheme employs Irregular Convolutional Codes (IrCC), Irregular Unity-Rate Codes (IrURC) and Irregular Mappers (IrMapper)
Low latency low power bit flipping algorithms for LDPC decoding
Full text linkLow Density Parity Check (LDPC) codes have been adopted in a number of wired and wireless communication standards due to their improved error correcting ability and relatively simple decoder structure. However, for very high throughput systems operating in the multi-Gb/s range conventional decoding methods based on message passing are limited, due largely to the sheer volume of messages being exchanged. Thus, simpler decoding methods have been proposed such as bit flipping permitting efficient and fast hardware implementation. This paper presents two new bit flipping algorithm designed to reduce latency and power consumption. For a small loss in bit error rate performance (0.5 dB) we show how the application of an early stopping criteria uses 89% fewer iterations compared to a similar published algorithm. We also present a method for reducing power consumption by placing processing elements into a quiescent state based on a bit-local metric. Using this technique we show a potential reduction in power consumption of 76%.Low Density Parity Check (LDPC) codes have been adopted in a number of wired and wireless communication standards due to their improved error correcting ability and relatively simple decoder structure. However, for very high throughput systems operating in the multi-Gb/s range conventional decoding methods based on message passing are limited, due largely to the sheer volume of messages being exchanged. Thus, simpler decoding methods have been proposed such as bit flipping permitting efficient and fast hardware implementation. This paper presents two new bit flipping algorithm designed to reduce latency and power consumption. For a small loss in bit error rate performance (0.5 dB) we show how the application of an early stopping criteria uses 89% fewer iterations compared to a similar published algorithm. We also present a method for reducing power consumption by placing processing elements into a quiescent state based on a bit-local metric. Using this technique we show a potential reduction in power consumption of 76%
Las nuevas tecnologías y el cerebro del futuro
Full text linkBit&Byte dialogó con el Dr. Facundo Manes y con el Dr. Mateo Niro.Facultad de Informátic
Bit-level pipelined digit-serial array processors
No full textA new architecture for high performance digit-serial vector inner product (VIP) which can be pipelined to the bit-level is introduced. The design of the digit-serial vector inner product is based on a new systematic design methodology using radix-2n arithmetic. The proposed architecture allows a high level of bit-level pipelining to increase the throughput rate with minimum initial delay and minimum area. This will give designers greater flexibility in finding the best tradeoff between hardware cost and throughput rate. It is shown that sub-digit pipelined digit-serial structure can achieve a higher throughput rate with much less area consumption than an equivalent bit-parallel structure. A twin-pipe architecture to double the throughput rate of digit-serial multipliers and consequently that of the digit-serial vector inner product is also presented. The effect of the number of pipelining levels and the twin-pipe architecture on the throughput rate and hardware cost are discussed. A two's complement digit-serial architecture which can operate on both negative and positive numbers is also presented
Designing embedded systems with 32-bit PIC microcontrollers and MikroC /
No full textThe new generation of 32-bit PIC microcontrollers can be used to solve the increasingly complex embedded system design challenges faced by engineers today. This book teaches the basics of 32-bit C programming, including an introduction to the PIC 32-bit C compiler. It includes a full description of the architecture of 32-bit PICs and their applications, along with coverage of the relevant development and debugging tools. Through a series of fully realized example projects, Dogan Ibrahim demonstrates how engineers can harness the power of this new technology to optimize their embedded design.Online resource; title from PDF title page (ebrary, viewed September 16, 2013).Front Cover; Designing Embedded Systems with 32-Bit PIC Microcontrollers and MikroC; Copyright; Contents; Preface; Acknowledgments; Chapter 1 -- Microcomputer Systems; 1.1 Introduction; 1.2 Microcontroller Systems; 1.3 Microcontroller Features; 1.4 Microcontroller Architectures; 1.5 8, 16, or 32Bits?; 1.6 Number Systems; 1.7 Converting Binary Numbers into Decimal; 1.8 Converting Decimal Numbers into Binary; 1.9 Converting Binary Numbers into Hexadecimal; 1.10 Converting Hexadecimal Numbers into Binary; 1.11 Converting Hexadecimal Numbers into Decimal.1.12 Converting Decimal Numbers into Hexadecimal1.13 Converting Octal Numbers into Decimal; 1.14 Converting Decimal Numbers into Octal; 1.15 Converting Octal Numbers into Binary; 1.16 Converting Binary Numbers into Octal; 1.17 Negative Numbers; 1.18 Adding Binary Numbers; 1.19 Subtracting Binary Numbers; 1.20 Multiplication of Binary Numbers; 1.21 Division of Binary Numbers; 1.22 Floating Point Numbers; 1.23 Converting a Floating Point Number into Decimal; 1.24 Binary Coded Decimal Numbers; 1.25 The American Standard Code for Information Interchange Table; 1.26 Summary; 1.27 Exercises.Chapter 2 -- PIC32 Microcontroller Series2.1 The PIC32MX360F512L Architecture; 2.2 Summary; 2.3 Exercises; Chapter 3 -- C Programming for 32-Bit PIC Microcontrollers; 3.1 Structure of a Simple mikroC Pro for PIC32 Program; 3.2 Functions; 3.3 PIC32 Microcontroller Specific Features; 3.4 Summary; 3.5 Exercises; Chapter 4 -- mikroC Pro for PIC32 Built-in Library Functions; 4.1 ADC Library; 4.2 LCD Library; 4.3 Software UART Library; 4.4 Hardware UART Library; 4.5 Sound Library; 4.6 ANSI C Library; 4.7 Miscellaneous Library; 4.8 Summary; 4.9 Exercises.Chapter 5 -- PIC32 Microcontroller Development Tools5.1 Software Development Tools; 5.2 Hardware Development Tools; 5.3 mikroC Pro for PIC32 IDE; 5.4 Summary; 5.5 Exercises; Chapter 6 -- Microcontroller Program Development; 6.1 Using the Program Description Language and Flowcharts; 6.2 Examples; 6.3 Representing for Loops in Flowcharts; 6.4 Summary; 6.5 Exercises; Chapter 7 -- Simple PIC32 Microcontroller Projects; 7.1 Project 7.1-LED DICE; 7.2 Project 7.2-Liquid-Crystal Display Event Counting; 7.3 Project 7.3-Creating a Custom LCD Character; 7.4 Project 7.4-LCD Progress Bar.7.5 Project 7.5-Shifting Text on LCD7.6 Project 7.6-External Interrupt-Based Event Counting Using LCD; 7.7 Project 7.7-Switch Contact Debouncing; 7.8 Project 7.8-Timer Interrupt-Based Counting; 7.9 Project 7.9-Temperature Measurement and Display on LCD; 7.10 Project 7.10-Playing a Melody; 7.11 Project 7.11-Playing a Melody Using Push-Button Switches; 7.12 Project 7.12-Generating Sine Wave Using D/A Converter; 7.13 Project 7.13-Communicating with a PC Using the RS232 PORT; 7.14 Project 7.14-Scrolling LCD Display; Chapter 8 -- Advanced PIC32 Projects.The new generation of 32-bit PIC microcontrollers can be used to solve the increasingly complex embedded system design challenges faced by engineers today. This book teaches the basics of 32-bit C programming, including an introduction to the PIC 32-bit C compiler. It includes a full description of the architecture of 32-bit PICs and their applications, along with coverage of the relevant development and debugging tools. Through a series of fully realized example projects, Dogan Ibrahim demonstrates how engineers can harness the power of this new technology to optimize their embedded design.Elsevie
Adaptive minimum bit-error-rate filtering
No full textAdaptive filtering has traditionally been developed based on the minimum mean square error (MMSE) principle and has found ever-increasing applications in communications. The paper develops adaptive filtering based on an alternative minimum bit error rate (MBER) criterion for communication applications. It is shown that the MBER filtering exploits the non-Gaussian distribution of filter output effectively and, consequently, can provides significant performance gain in terms of smaller bit error error (BER) over the MMSE approach. Adopting the classical Parzen window or kernel density estimation for a probability density function (p.d.f.), a block-data gradient adaptive MBER algorithm is derived. A stochastic gradient adaptive MBER algorithm is further developed for sample-by-sample adaptive implementation of the MBER filtering. Extension of the MBER approach to adaptive nonlinear filtering is also discussed
Desarrollos tecnológicos
Full text linkBit&Byte destina este espacio para compartir con sus lectores algunas de las innovaciones tecnológicas que se han desarrollado en diferentes países del mundo durante los primeros meses del año.Facultad de Informátic
Un equipo de trabajo en una Facultad que crece constantemente
Full text linkLaura Nievas, Julieta Castelli, Alejandra Pizarro y Fernanda Aday, forman parte de la planta no docente de la Facultad de Informática desde antes de su creación. En una charla con Bit&Byte, repasaron el crecimiento que tuvo la Facultad a partir de aquel momento y contaron cómo afecta el uso de las tecnologías en las tareas administrativas.Facultad de Informátic
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