1,721,190 research outputs found
Network Interface Architecture and Design Issues
No full textThis chapter addresses NI architecture and design issues, leveraging
a number of case studies. It presents interface protocols at the frontend
of NI architectures as the result of a long evolutionary path of SoC
communication protocols. Moreover, it shows some implementation
approaches to packetization, from traditional wrapper-based solutions up
to the potential solutions opened by the latest developments in processor
interfaces. This chapter then analyzes the impact that design choices
taken at the NI might have on system-level performance, area and power:
from packet size and flit width all the way to flow control schemes and
switching techniques. Finally, three representative case studies are
presented, addressing design issues of NIs for QoS-oriented, BE, and asynchronous
NoCs. Through the area and power breakdown of NI prototypes,
the reader is able to understand where complexity arises in the
architecture, and is led to assess the fraction of area and power NIs
consume in real platform implementations using NoCs
An Interconnect-Centric Approach to the Flexible Partitioning and Isolation of Many-Core Accelerators for Fog Computing
No full textFog computing platforms are currently challenged by new design requirements: low-overhead sharing mechanisms among Internet-of-Things (IoT) services, the strong isolation of their execution environments and adaptive resource allocation to them, matching the inherent dynamic nature of most IoT applications. This paper targets the fulfillment of these requirements in a many-core programmable accelerator for future Fog computing nodes by leveraging the pivotal role played by the on-chip communication architecture for efficient, flexible and secure sharing of the whole device
The Data Link Layer in NoC Design
No full textThis chapter provides a comprehensive overview of data-link layer design
issues in the NoC domain. This layer is in charge of implementing a
technology-independent approach to communication reliability and of exposing
a reliable communication channel in spite of the underlying unreliable
medium. The increased sensitivity of interconnects to on-chip noise
sources will make an efficient data-link layer architecture critical for the
success of NoCs
Designing Network On-Chip Architectures in the Nanoscale Era
No full textThe editors view an ongoing development effort of NoC architectures toward an increased dynamism and flexibility as headed to a new milestone for NoC technology. The book does not intend to miss the opportunity to join this exciting ride, and presents in a coherent and systematic fashion both stabilized and less stabilized topics, with the level of detail enabled by their state-of-the-art, thus hopefully helping understand what is going on in the NoC community and serving as stepping stone into future chip multiprocessor architectures
Battery Lifetime Optimization for Energy-Aware Circuits
No full textThe power consumption of integrated circuits is one of the most problematic considerations affecting the design of high-performance chips and portable devices. The study of power-saving design methodologies now must also include subjects such as systems on chips, embedded software, and the future of microelectronics. Low-Power Electronics Design covers all major aspects of low-power design of ICs in deep submicron technologies and addresses emerging topics related to future design. This volume explores, in individual chapters written by expert authors, the many low-power techniques born during the past decade. It also discusses the many different domains and disciplines that impact power consumption, including processors, complex circuits, software, CAD tools, and energy sources and management. The authors delve into what many specialists predict about the future by presenting techniques that are promising but are not yet reality. They investigate nanotechnologies, optical circuits, ad hoc networks, e-textiles, as well as human powered sources of energy. Low-Power Electronics Design delivers a complete picture of today's methods for reducing power, and also illustrates the advances in chip design that may be commonplace 10 or 15 years from now
Design Space Exploration of Wavelength-Routed Optical NoC Topologies for 3D-Stacked Multi- and Many-Core Processors.
No full text1) Introduction
2) Silicon Photonics as a Technology Enabler
2a) Optical Links
2b) Modulators
2c) Photonic-Switching Elements and Optical Routers for Optical Networks-on-Chip
2d) Photodetectors
2e) Laser Sources
3) Need for Pathfinding
4) Predictability-Critical ONoC Topologies
5) Design Space Exploration of Wavelength-Routed Topologies
5a) Global Connectivity
5b) Network Partitioning
5c) Comparison with an Optical Ring Topology
5d) Network Partitioning
5f) Logic Topologies
5e) Physical Topologies
5g) Power Efficiency of Topologies
5h) Global Connectivity vs. Network partitioning
6) Spatial-Division-Multiplexing Ring Topology vs. Filter-based Topology
7) Conclusion
8) Reference
Understanding the Design Space of Wavelength-Routed Optical NoC Topologies for Power-Performance Optimization
No full textSilicon photonics is the most promising emerging technology to deliver on- and off-chip communication performance and power that vastly exceed the capabilities of electronics. However, a significant abstraction gap does exist between novel devices and circuits and the higher-order switching structures that system designers need to instantiate. Currently, designers mostly rely on their intuition to bridge this abstraction gap. This paper lays the groundwork for a more rigorous and effective approach, by vertically-integrating the most advanced design methods and tools for topology synthesis and refinement in the context of a novel performance analysis framework. As a result, we can extract the highest aggregate bandwidth out of an optical network-on-chip topology, and provide an early-stage analysis of its static power, thus unveiling unexplored portions of the design space and interpreting its characteristics
A retrospective look at xpipes: The exciting ride from a design experience to a design platform for nanoscale networks-on-chip
No full textThis paper provides a retrospective look at the xpipes framework, and documents its evolution from a promising network-on-chip (NoC) design experience to a comprehensive design platform for the next-generation of nanoscale NoCs. Since the early days of xpipes, its cross-layer approach to NoC design has fostered the development and maturity of circuits, architectures and design flows, thus rapidly bridging the gap between the NoC concept and viable interconnect technology for industrial uptake
Xpipes: a network-on-chip architecture for gigascale systems-on-chip
No full textThe growing complexity of embedded multiprocessor architectures for digital media processing will soon require highly scalable communication infrastructures. Packet switched networks-on-chip (NoC) have been proposed to support the trend for systems-on-chip integration. In this paper, an advanced NoC architecture, called Xpipes, targeting high performance and reliable communication for on-chip multi-processors is introduced. It consists of a library of soft macros (switches, network interfaces and links) that are design-time composable and tunable so that domain-specific heterogeneous architectures can be instantiated and synthesized. Links can be pipelined with a flexible number of stages to decouple link throughput from its length and to get arbitrary topologies. Moreover, a tool called XpipesCompiler, which automatically instantiates a customized NoC from the library of soft network components, is used in this paper to test the Xpipes-based synthesis flow for domain-specific communication architectures
- …
