1,615 research outputs found
Switch Architecture
No full textThis chapter reviews the main architecture design techniques for network-on-chip switches. It recalls many principles from the general theory of off-chip interconnection networks, but provides thorough insights on the design principles and guidelines specifically for on-chip networks. After reading the chapter, the reader will understand in how many ways NoCs are fundamentally different from off-chip networks, due to more stringent resource budgets
Topology Exploration
No full textThe topology is a key factor for the performance and cost of any network-on-chip. Quality metrics and even feasibility of topologies are extremely sensitive to the performance of on-chip interconnects and to similar sutble design issues, with deep implications on the network architecture as well. This chapter moves from the awareness that many regular topologies feature better abstract properties than a 2-D mesh, however their silicon implementation is very challenging. The objective of this chapter is to quantify to which extent their inherently better abstract properties are impacted by the degradation effects of the physical implementation on nanoscale silicon technologies
The Synchronization Challenge
No full textSynchronization is today among the most critical challenges in the design of a global on-chip communication infrastructure,as emerging variability, signal integrity, power dissipation limits are contributing toa severe break-down of the global synchronicity assumption when a logical structure spans more than a couple of millimiters on a die. This chapter addressed globally asynchronous and locally synchronous architectures with emphasis on the implications for the communication fabric of largely integrated multicore systems
Understanding the Design Space of Wavelength-Routed Optical NoC Topologies for Power-Performance Optimization
No full textSilicon photonics is the most promising emerging technology to deliver on- and off-chip communication performance and power that vastly exceed the capabilities of electronics. However, a significant abstraction gap does exist between novel devices and circuits and the higher-order switching structures that system designers need to instantiate. Currently, designers mostly rely on their intuition to bridge this abstraction gap. This paper lays the groundwork for a more rigorous and effective approach, by vertically-integrating the most advanced design methods and tools for topology synthesis and refinement in the context of a novel performance analysis framework. As a result, we can extract the highest aggregate bandwidth out of an optical network-on-chip topology, and provide an early-stage analysis of its static power, thus unveiling unexplored portions of the design space and interpreting its characteristics
A retrospective look at xpipes: The exciting ride from a design experience to a design platform for nanoscale networks-on-chip
No full textThis paper provides a retrospective look at the xpipes framework, and documents its evolution from a promising network-on-chip (NoC) design experience to a comprehensive design platform for the next-generation of nanoscale NoCs. Since the early days of xpipes, its cross-layer approach to NoC design has fostered the development and maturity of circuits, architectures and design flows, thus rapidly bridging the gap between the NoC concept and viable interconnect technology for industrial uptake
Network Interface Architecture and Design Issues
No full textThis chapter addresses NI architecture and design issues, leveraging
a number of case studies. It presents interface protocols at the frontend
of NI architectures as the result of a long evolutionary path of SoC
communication protocols. Moreover, it shows some implementation
approaches to packetization, from traditional wrapper-based solutions up
to the potential solutions opened by the latest developments in processor
interfaces. This chapter then analyzes the impact that design choices
taken at the NI might have on system-level performance, area and power:
from packet size and flit width all the way to flow control schemes and
switching techniques. Finally, three representative case studies are
presented, addressing design issues of NIs for QoS-oriented, BE, and asynchronous
NoCs. Through the area and power breakdown of NI prototypes,
the reader is able to understand where complexity arises in the
architecture, and is led to assess the fraction of area and power NIs
consume in real platform implementations using NoCs
Performance, Area and Power Breakdown Analysis for NoC switches in 65nm technology
No full textLeveraging a development effort of the synthesis backend for Networks-on-Chip (NoCs), this work
contributes an analysis of the performance, area and power/energy breakdown of NoC switches in 65nm
technology. In particular, an architecture-level technique (control- and data-path decoupling) is deployed
to derive switch implementation variants optimized for different design objectives, and is then
validated against placement-aware logic synthesis
The Design Predictability Concern in Optical Network-on-Chip Design
No full textPredictability is a well-known concern for electronic circuit design. This paper shows that it is a concern for optical network-on-chip design too. The gap between logic and physical topologies is used as a case study. © OSA 2012
NoC-centric partitioning and reconfiguration technologies for the efficient sharing of multi-core programmable accelerators
No full textToday, multi- and many-core architectures are gaining momentum as a potential source of hardware acceleration, bringing to new challenges for system designers related to both system virtualization and runtime testing. Our research activity tackles these challenges exploiting and optimizing the capabilities of reconfiguring the routing function at runtime
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