1,721,976 research outputs found
Granelli Benini L. — Introduzione alla demografia storica
No full textHoudaille Jacques. Granelli Benini L. — Introduzione alla demografia storica. In: Population, 31ᵉ année, n°3, 1976. p. 740
Granelli Benini L. — Introduzione alla demografia storica
No full textHoudaille Jacques. Granelli Benini L. — Introduzione alla demografia storica. In: Population, 31ᵉ année, n°3, 1976. p. 740
Dynamic Power Management of Streaming Applications over a Wireless LAN
No full textDesigning wireless streaming multimedia applications is a challenging task that involves the exploration of multiple parameters subject to real-time constraints. In particular, battery-powered multimedia appliances must provide a target quality of service (QoS) level within a limited energy and resource budget. In this work we address the problem of reducing the power consumption of the network interface card (NIC) when accessing a streaming video from a mobile client. We explore the opportunities for power reduction offered by traffic reshaping performed at both MAC-level and application-level. At MAC level, we exploit the degrees of freedom offered by the IEEE 802.11b power management. At application level we propose a new client-driven DPM policy. The proposed approaches have been validated using both real-world measurements, performed on instrumented fully-operational equipments, and accurate power simulations, performed using ad-hoc simulation models built on top of MathWorks' Simulink. Simulation models were characterized and validated against real-world measurements, and used to explore design choices not-yet supported by the commercial implementations of the IEEE 802.11b protocol. Experimental results show that the proposed approach allows us to save more than 60% of the energy consumption of the wireless NIC without any performance penalty
Secure Near-Sensor Analytics: the PULP approach
No full textNear-sensor processing is needed in numerous IoT application Scenarios, where communication of raw sensor data is neither affordable nor secure. In this talk I will give an overview on how to address the challenge of pushing data analytics and security at the sensors sites using a Parallel Ultra-Low Power (PULP) heterogeneous computing approach
Optimizing Offload Performance in Heterogeneous MPSoCs
No full textHeterogeneous multi-core architectures combine a few 'host' cores, optimized for single-thread performance, with many small energy-efficient 'accelerator' cores for data-parallel processing, on a single chip. Offloading a computation to the many-core acceleration fabric introduces a communication and synchronization cost which reduces the speedup attainable on the accelerator, particularly for small and fine-grained parallel tasks. We demonstrate that by co-designing the hardware and offload routines, we can increase the speedup of an offloaded DAXPY kernel by as much as 47.9%. Furthermore, we show that it is possible to accurately model the runtime of an offloaded application, accounting for the offload overheads, with as low as 1% MAPE error, enabling optimal offload decisions under offload execution time constraints
Efficient OpenMP support and extensions for MPSoCs with explicitly managed memory hierarchy
No full textAbstract—OpenMP is a de facto standard interface of the shared
address space parallel programming model. Recently, there have been
many attempts to use it as a programming environment for embedded
MultiProcessor Systems-On-Chip (MPSoCs). This is due both to the ease
of specifying parallel execution within a sequential code with OpenMP
directives, and to the lack of a standard parallel programming method
on MPSoCs. However, MPSoC platforms for embedded applications
often feature non-uniform, explicitly managed memory hierarchies with
no hardware cache coherency as well as heterogeneous cores with
heterogeneous run-time systems.
In this paper we present an optimized implementation of the compiler
and runtime support infrastructure for OpenMP programming for a
non-cache-coherent distributed memory MPSoC with explicitly managed
scratchpad memories (SPM). The proposed framework features specific
extensions to the OpenMP programming model that leverage explicit
management of the memory hierarchy. Experimental results on different
real-life applications confirm the effectiveness of the optimization in terms
of performance improvements
Robust RTL Power Macromodels
No full textIn this paper, we propose a robust register-transfer level (RTL) power modeling methodology for functional units.
Our models are consistently accurate over a wide range of input statistics, they are automatically constructed and can provide pattern-by-pattern power estimates. An additional desirable feature of our modeling methodology is the capability of accounting for the impact of technology variations, library changes and synthesis tools. Our methodology is based on the concept of node sampling, as opposed to more traditional approaches based on input sampling
An OpenMP Compiler for Efficient Use of Distributed Scratchpad Memory in MPSoCs
No full textMost of today’s state-of-the-art processors for mobile and embedded systems feature on-chip scratchpad memories. To
efficiently exploit the advantages of low-latency high-bandwidth memory modules in the hierarchy, there is the need for programming
models and/or language features that expose such architectural details. On the other hand, effectively exploiting the limited on-chip
memory space requires the programmer to devise an efficient partitioning and distributed placement of shared data at the application
level. In this paper, we propose a programming framework that combines the ease of use of OpenMP with simple, yet powerful,
language extensions to trigger array data partitioning. Our compiler exploits profiled information on array access count to automatically
generate data allocation schemes optimized for locality of references
RISC-V for Real-time MCUs - Software Optimization and Microarchitectural Gap Analysis
No full textProcessors using the RISC-VISA are finding increasing real use in IoT and embedded systems in the MCU segment. However, many real-life use cases in this segment have realtime constraints. In this paper we analyze the current state of real-time support for RISC-V with respect to the ISA, available hardware and software stack focusing on the RV32IMC subset of the ISA. As a reference point, we use the CV32E40P, an open-source industrially supported RV32IMFC core and FreeRTOS, a popular open-source real-time operating system, to do a baseline characterization. We perform a series of software optimizations on the vanilla RISC-V FreeRTOS port where we also explore and make use of ISA and micro-architectural features, improving the context switch time by 25% and the interrupt latency by 33% in the average and 20% in the worst-case run on a CV32E40P when evaluated on a power control unit firmware and synthetic benchmarks. This improved version serves then in a comparison against the ARM Cortex-M series, which in turn allows us to highlight gaps and challenges to be tackled in the RISC-VISA as well as in the hardware/software ecosystem to achieve competitive maturity
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