5,281 research outputs found
Automated DNA Fragments Recognition and Sizing through AFM Image Processing
Full text linkThis paper presents an automated algorithm to determine DNA fragment size from atomic force microscope images and to extract the molecular profiles. The sizing of DNA fragments is a widely used procedure for investigating the physical properties of individual or protein-bound DNA molecules. Several atomic force microscope (AFM) real and computer-generated images were tested for different pixel and fragment sizes and for different background noises. The automated approach minimizes processing time with respect to manual and semi-automated DNA sizing. Moreover, the DNA molecule profile recognition can be used to perform further structural analysis. For computer-generated images, the root mean square error incurred by the automated algorithm in the length estimation is 0.6% for a 7.8 nm image pixel size and 0.34% for a 3.9 nm image pixel size. For AFM real images we obtain a distribution of lengths with a standard deviation of 2.3% of mean and a measured average length very close to the real one, with an error around 0.33%
Designing next-generation smart sensor hubs for the Internet-of-Things5th IEEE International Workshop on Advances in Sensors and Interfaces IWASI
No full textMaterializing the vision and the huge business opportunities offered by the Internet-of-Things requires a
paradigm shift in sensor data processing, fusing, understanding. Centralized approaches (sensors at the
edges, with centralized intelligence in the cloud) are not scalable, hierarchical, distributed processing is a
strong requirement. In this talk I will describe recent trends in the development of new computing
platforms geared to distributed sensor data management, discuss design challenges and research
opportunities
Sub-PicoJoule per operation scalable computing
No full textThe "internet of everything" envisions trillions of connected objects loaded with high-bandwidth sensors requiring massive amounts of local signal processing, fusion, pattern extraction and classification. From the computational viewpoint, the challenge is formidable and can be addressed only by pushing computing fabrics toward massive parallelism and brain-like energy efficiency levels. CMOS technology can still take us a long way toward this vision. Our recent results with the open-source PULP (parallel ultra-low power) chips demonstrate that pj/OP (GOPS/mW) computational efficiency is within reach in today's 28nm CMOS FDSOI technology. In this talk, I will look at the next 1000x of energy efficiency improvement, which will require heterogeneous 3D integration, mixed-signal, approximate processing and non-Von-Neumann architectures for scalable acceleration
Plenty of room at the bottom? Micropower deep learning for cognitive cyber physical systems
No full textSummary form only given. Deep convolutional neural networks are being regarded today as an extremely effective and flexible approach for extracting actionable, high-level information from the wealth of raw data produced by a wide variety of sensory data sources. CNNs are however computationally demanding: today they typically run on GPU-accelerated compute servers or high-end embedded platforms. Industry and academia are racing to bring CNN inference (first) and training (next) within ever tighter power envelopes, while at the same time meeting real-time requirements. Recent results, including our PULP and ORIGAMI chips, demonstrate there is plenty of room at the bottom: pj/OP (GOPS/mW) computational efficiency, needed for deploying CNNs in the mobile/wearable scenario, is within reach. However, this is not enough: 1000x energy efficiency improvement, within a mW power envelope and with low-cost CMOS processes, is required for deploying CNNs in the most demanding CPS scenarios. The fj/OP milestone will require heterogeneous (3D) integration with ultra-efficient die-to-die communication, mixed-signal pre-processing, event-based approximate computing, while still meeting real-time requirements
PROGETTO SOGGETTO Premio critica Web per aver totalizzato il maggior numero di voti
No full textIl cortometraggio dal titolo “Il Volto e l’architetto” con la regia di Pietro Davide Jona Lasinio, prodotto da Stefano Misiani, sceneggiatura di Monica Testi, Roberto Benini, Luca Ribichini e Pietro Jona,
propone una affascinante ipotesi di una relazione tra le linee della pianta della villa dei tracciati proporzionali di un volto femminile.
Tale idea è tratta dal libro “Il volto e l’architetto” di Luca Ribichini dove si rivela una visione armoniosa ed inedita dell’opera di Le Corbusie
Concorso PROGETTO-SOGGETTO, concorso per cortometraggi dedicati all’Architettura, organizzato da Architettura e Critica: PREMIO SPECIALE DELLA GIURIA PER LA QUALITA' DELL'OPERA .
No full textIl cortometraggio dal titolo “Il Volto e l’architetto” con la regia di Pietro Davide Jona Lasinio, prodotto da Stefano Misiani, sceneggiatura di Monica Testi, Roberto Benini, Luca Ribichini e Pietro Jona,
propone una affascinante ipotesi di una relazione tra le linee della pianta della villa dei tracciati proporzionali di un volto femminile.
Tale idea è tratta dal libro “Il volto e l’architetto” di Luca Ribichini dove si rivela una visione armoniosa ed inedita dell’opera di Le Corbusie
Message from the Chairs
No full textWelcome to the 8th IEEE/ACM International Symposium on Networks-on-Chip (NOCS). NOCS is the pre- mier event dedicated to interdisciplinary research on Networks-on-Chip innovations. It is a unique venue that brings together scientists and engineers from diverse, but inter-related research communities, including computer architecture, general networking, circuits and systems, embedded systems, and design automation
Origami: A 803-GOp/s/W Convolutional Network Accelerator
Full text linkAn ever-increasing number of computer vision and image/video processing challenges are being approached using deep convolutional neural networks, obtaining state-of-the-art results in object recognition and detection, semantic segmentation, action recognition, optical flow, and super resolution. Hardware acceleration of these algorithms is essential to adopt these improvements in embedded and mobile computer vision systems. We present a new architecture, design, and implementation, as well as the first reported silicon measurements of such an accelerator, outperforming previous work in terms of power, area, and I/O efficiency. The manufactured device provides up to 196 GOp/s on 3.09 mm2 of silicon in UMC 65-nm technology and can achieve a power efficiency of 803 GOp/s/W. The massively reduced bandwidth requirements make it the first architecture scalable to TOp/s performance
PULP: Extreme Energy Efficiency for Extreme Edge AI Acceleration
No full textThe next wave of pervasive AI pushes machine learning (ML) acceleration toward the extreme edge, with
mW powerbudgets, while atthe same time it raisesthebar in terms of accuracy and capabilities, with new ML models being
propose on a daily basis. To succeed in this balancing act, we need principled ways to walk the line between flexible and
highly specialized ML acceleration architectures. In this talk I will detail on how to walk the line, drawing from the
experience of the open PULP (Parallel Ultra-Low Power) platform, based on ML-enhanced RISC-V processors coupled
with domain-specific acceleration engines
From Nano-Drones to Cars - A RISC-V Open Platform for next-generation Vehicles
No full textThe next generation of highly autonomous vehicles, with form factors ranging from tiny palmsized drones to cars pushes signal processing and machine learning aggressively towards the edge, near sensors and actuators, with strong energy-efficiency, safety and security requirements, while at the same time raising the bar in terms of flexibility and performance. To succeed in this balancing act, we need principled ways to walk the line between conflicting non-functional requirements. In the talk, I will describe our experience in leveraging the Open RISC-V ISA and open hardware approaches to innovate across the board and pave the way for an open embedded computing platform for autonomous vehicles
- …
