1,721,114 research outputs found
Dataset supporting: A sub-nW/kHz Relaxation Oscillator with Ratioed Reference and sub-Clock Power Gated Comparator
No full textMeasured data for results presented in the paper: "A sub-nW/kHz Relaxation Oscillator with Ratioed Reference and sub-Clock Power Gated Comparator" to be published in Journal of Solid State Circuits (JSSC) authored by Anand Savanth, Alex S. Weddell, James Myers, David Flynn and Bashir M. Al-Hashimi</span
VHDL-AMS implementation of a numerical ballistic CNT model for logic circuit simulation
No full textThis paper introduces a novel numerical carbon nanotube transistor (CNT) modelling approach which brings in a flexible and efficient cubic spline non-linear approximation of the non-equilibrium mobile charge density. The spline algorithm creates a rapid and accurate solution of the numerical relationship between the charge density and the self-consistent voltage, which leads to the speed-up of deriving the current through the channel without losing much accuracy. This modelling method also allows the flexibility of choosing different cubic spline intervals which may affect the performance of the model, but it is still capable of obtaining an acceleration of more than a 100 times while maintaining the accuracy within less than 1.5% normalised RMS error compared with previous reported theoretical modelling approach. The model has been proved working as transistors in a logic inverter implemented using VHDL-AMS and simulated in SystemVision, which shows the availability of implementing a circuit-level simulators with our proposed model. Additionally, although this model is originally based on the ideal ballistic transport characteristics, it shows good flexibility that the extension with numbers of non-ballistic features are certainly acceptable
Efficient circuit-level modelling of ballistic CNT using piecewise non-linear approximation of mobile charge density
Full text linkThis paper presents a new carbon nanotube transistor (CNT) modelling technique which is based on an efficient numerical piece-wise non-linear approximation of the non-equilibrium mobile charge density. The technique facilitates the solution of the self-consistent voltage equation in a carbon nanotube such that the CNT drain-source current evaluation is accelerated by more than three orders of magnitude while maintaining high modelling accuracy. The model is currently limited to ballistic transport but can be extended to non-ballistic modes of transport when a suitable theory is developed while researchers study phenomena that sometimes prevent electrons in a carbon nanotube from going ballistic. Our results show that while the accuracy and speed of the proposed model vary with the number of piece-wise segments in the mobile charge approximation, it is possible to obtain a speed-up of more than 1000 times while maintaining the accuracy within less than 2% in terms of average RMS error compared with the state of the art theoretical reference CNT model implemented in FETToy. This numerical efficiency makes our model particularly suitable for implementation in circuit-level, eg. SPICE-like, simulators where large numbers of such devices may be used to build complex circuits
A Survey of Multi-Source Energy Harvesting Systems
No full textEnergy harvesting allows low-power embedded devices to be powered from naturally-occurring or unwanted environmental energy (e.g. light, vibration, or temperature difference). While a number of systems incorporating energy harvesters are now available commercially, they are specific to certain types of energy source. Energy availability can be a temporal as well as spatial effect. To address this issue, ‘hybrid’ energy harvesting systems combine multiple harvesters on the same platform, but the design of these systems is not straightforward. This paper surveys their design, including trade-offs affecting their efficiency, applicability, and ease of deployment. This survey, and the taxonomy of multi-source energy harvesting systems that it presents, will be of benefit to designers of future systems. Furthermore, we identify and comment upon the current and future research directions in this field
Test Strategies for Multi-Voltage Designs
Full text linkReducing the power consumption of digital designs through the use of more than one Vdd value (Multi-Voltage) is known and well practiced. Some manufacturing defects have Vdd-dependency, which implies defects can become active only at certain power supply setting, leading to reduced defect coverage. This chapter presents a coherent overview of recently reported research in testing strategies for multi-voltage designs including defect modelling, test generation and DFT solutions. The chapter also outlines number of worthy research problems that need to be addressed to develop high quality and cost effective test solutions for multi-Vdd designs
Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture
No full textWe propose two new repair techniques for hybrid nano/CMOS computing architecture with lookup table based Boolean logic. Our proposed techniques use tagging mechanism to provide high level of defect tolerance and we present theoretical equations to predict the repair capability including an estimate of the repair cost. The repair techniques are efficient in utilization of spare units and capable of targeting upto 20% defect rates, which is higher than recently reported repair techniques
Network-on-chip architectures and design methods
No full textSystem-on-Chip (SoC) represents the next major market for microelectronics, and there is considerable interest world-wide in developing effective methods and tools to support the SoC paradigm. SoC is an expanding field, at present the technical and technological literature about the overall state-of-the-art in SoC is dispersed across a wide spectrum which includes books, journals, and conference proceedings. The book provides a comprehensive and accessible source of state-of-the-art information on existing and emerging SoC key research areas, provided by leading experts in the field. This book covers the general principles of designing, validating and testing complex embedded computing systems and their underlying tradeoffs. The book has twenty five chapters organised into eight parts, each part focuses on a particular topic of SoC. Each chapter has some background covering the basic principles, and extensive list of references. It is aimed at graduate students,! designers and managers working in Electronic and Computer engineering
Dataset for Arbitrarily Parallel Turbo Decoding for Ultra-Reliable Low Latency Communication in 3GPP LTE
No full textThis dataset supports the publication:
Luping Xiang, Matthew Brejza, Robert G. Maunder, Bashir M. Al-Hashimi and Lajos Hanzo;
Arbitrarily Parallel Turbo Decoding for Ultra-Reliable Low Latency Communication in 3GPP LTE.
IEEE Journal on Selected Areas in Communications
This dataset contains which are used for generating Fig.6 Fig.10 Fig.11 and Fig.12. These figures are plotted using GLE (Graphics Layout Engine). The scripts of Gle are also included in the folds for each figures. see ReadMe file for more information.
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