196,030 research outputs found
Comparison of BULK and Ultra-Thin Double Gate SOI MOSFETs for the 65 nm Technology Node: A Monte Carlo Study
No full text
Comparative analysis of self-heating in different SOI architectures
No full textIn this paper we apply 3D Drift Diffusion Electro-Thermal simulations to the analysis of SHE in different Silicon On Insulator structures, featuring the same isothermal electrical characteristics
Simulation of self-heating effects in different SOI MOS architectures
No full textThis contribution discusses Self-Heating effects in different SOI MOS architectures by 3-D electrothermal simulation and compares Planar Single Gate SOI, Double-Gate SOI and FinFETs.
The results of our simulations highlight the main dependences on the structural characteristics of the devices, of the impact of self-heating on electrical performance
AC and DC numerical simulation of Self–Heating Effects in FinFETs
No full textThis paper presents detailed DC and AC numerical simulations of thermal effects in nanoscale FinFET devices. Three–dimensional electro–thermal numerical simulations, including a realistic description of the source, drain and gate interconnections, are validated by comparison with DC I–V and AC small–signal parameters. The importance of a realistic description of the interconnects for the AC simulation of FinFETs is discussed
Analysis of Scaling Strategies for Sub-30 nm Double-Gate SOI N-MOSFETs
No full textState-of-the-art device simulation is applied to the
analysis of possible scaling strategies for the future CMOS technology,
adopting the ultrathin silicon body (UTB) double-gate
(DG) MOSFET and considering the main figures of merit (FOM)
for the high-performance N-MOS transistor. The results of our
analysis confirm the potentials of UTB-DG MOSFETs. In particular,
the possibility to control the short-channel effects by
thinning the silicon layer is fully exploited allowing to adopt
almost undoped silicon channel, leading to reduced transversal
field. As a consequence, the impact of surface roughness at the
Si-oxide interface and the gate tunneling leakage current are
substantially reduced compared to the case of highly doped bulk
MOSFETs. According to our results, thanks to the suppression of
gate leakage current, scaling of the UTB-DG MOSFET down to
the 32 nm technology node appears possible adopting SiO2-based
gate dielectrics. In spite of the improved mobility at given inversion
charge density, the simulated on-currents are substantially lower
than those required by the 2005 ITRS for the 45 and 32 nm nodes. Nonetheless, thanks to relaxed scaling of the oxide thickness,
hence to reduced gate capacitance, the requirements in terms of
intrinsic delay and power-delay product can be satisfied. The issue
of variability is analyzed by evaluating the dependence of the key
FOM on the variation of critical dimensions such as the thickness
of the gate oxide and of the silicon layer
Monte-Carlo Simulation of Decananometric nMOSFETs: Multi-Subband vs. 3D-Electron Gas with Quantum Corrections
No full textIn this paper two Monte-Carlo simulators implementing different models for the influence of carrier quantization on the electrostatics
and transport are used to analyze sub-100 nm double-gate SOI devices. To this purpose a new stable and efficient scheme to implement
the contacts in the simulation of double-gate SOI devices is introduced first. Then, results in terms of drain current and microscopic
quantities are compared, providing new insight on the limitation of a well assessed semiclassical transport simulation approach and a
more rigorous multi-subband model
Scaling the High-Performance Double-Gate SOI MOSFET down to the 32 nm Technology Node with SiO2-based Gate Stacks
No full textWe apply state-of-the-art simulation to investigate the possibility to scale the UTB-DG MOSFET using rather conventional SiO2-based dielectrics with a minimum thickness of 1 nm, a lower limit set by the need for process yield and reproducibility. The analysis include short-channel effects, gate leakage tunneling current, ON-current and the intrinsic switching delay-time CV/I
Simulation of Bulk and SOI Digital Circuits Including Self-Heating Effects
No full textWe study the impact of self-heating on device characteristics to compare advantages of double-gate silicon on insulator (DGSOI) over bulk technology.
Performance comparison of digital circuits like three stage ring oscillator has been made. Impact of self-heating on the performance of oscillator implemented
with SOI double gate FETs and bulkFETs has also been investigated. Although self-heating affects the performance of digital circuits for scaled SOI
technologies considerably due to poor thermal conductivity of the buried oxide layer, DGSOI circuits retain a significant advantage over bulk counterpart
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