1,720,982 research outputs found
Speeding up AES by extending a 32-bit processor instruction set
No full textNowadays the need of speed in cipher and decipher operations is more important than in the past. This is due to the diffusion of real time applications, which fact involves the use of cryptography. Many co-processors for cryptography were studied and presented in the past, but only few works were addressed to the enhancement of the instruction set architecture (ISA) of the embedded processor. This paper presents an extension of the ISA of a 32 bit processor, that aims at speeding up the software implementations of the AES algorithm. After the identification of the most frequently executed and the most time consuming sections of the algorithm, a set of dedicated instructions is designed in order to improve the performances of the cipher operations. We validate our instruction set extension by measuring the speed up for different optimized implementations of AES using an ARM processor simulator, but the enhancements we propose are general enough to be applied to almost all 32 bit processors
An efficient hardware-based fault diagnosis scheme for AES: performances and cost
No full textSince standardization in 2001, the Advanced Encryption Standard has been the subject of many research efforts, aimed at developing effcient hardware implementations with reduced area and latency. So far, reliability has not been considered a primary objective. Recently, several error detecting schemes have been proposed in order to provide some defense against hardware faults in AES. The benefits of such schemes are twofold: avoiding wrong outputs when benign hardware faults occur, and preventing the collection of information about the secret key through malicious injection of faults. In this paper, we present a complete scheme for parity-based fault detection in a hardware implementation of the Advanced Encryption Standard which includes a key schedule unit. We also provide a preliminary evaluation of the hardware and latency overhead of the proposed scheme
Procedimento e sistema per il calcolo del prodotto interno su campi di Galois
No full textCircuit for the inner or scalar product computation in Galois field
Comparative cost/performance evaluation of digit-serial multipliers for finite fields of type GF(2n)
No full textMultiplication in finite fields (Galois fields) is a basic operation for cryptography applications. Recent proposals for elliptic code cryptography, require efficient computation of multiplication in finite fields of type GF(2n) for large values of n (150, 200 bits). Digit-serial multiplier VLSI architectures are an attractive solution, being a compromise between purely parallel and serial ones. A comparative study of digit-serial multiplier VLSI architectures, for fields of type GF(2n), is carried out. Such architectures are reviewed, some further optimisations are proposed, and are then implemented in VHDL (CMOS cell library, 0.35 μm, by ST Microelectronics). Figures of merit like time latency, silicon area and power consumption are evaluated by simulation with Synopsis tools, varying parameters like the size n of the field elements and the size k of the blocks of bits being processed in parallel by the digit-serial architectures
Efficient finite field digit-serial multiplier architecture for cryptography applications
No full textCryptographic applications in embedded systems for smart-cards require low-latency, low-complexity and low power dedicated hardware. In this work the GBB algorithm for finite field multiplication is optimised by recoding and the related digit-serial VLSI multiplier architecture is designed and evaluated
Power aware design of an elliptic curve coprocessor for 8-bit platforms
No full textPublic key cryptography is widely considered as the best building block for key exchange; different public key algorithms are standardized and used in many applications. Among them, ECC (Elliptic Curve Cryptography) is considered the best solution in terms of security, computational requirements and storage need for secret and public keys. Energy consumption is among the main constraints to be considered in wireless sensor networks. In the case of sensor networks, the typical approaches of minimizing latency via a complete hardware coprocessor or reducing area overhead via an efficient implementation of finite field operations might not provide the best solution. In this paper a coprocessor for minimizing both additional resources and power consumption is presented for elliptic curve over binary extension fields, The costs and performances of such new coprocessors are compared with known results, showing that space exists for the reduction of energy consumption without degrading the other performance figures
A parallelized design for an elliptic curve cryptosystem coprocessor
No full textIn many applications a software implementation of ECC (elliptic curve cryptography) might be inappropriate due to performance requirements, therefore hardware implementations are needed. We present some results about a novel hardware implementation for ECC, that introduces also a form of parallelism to maximize the use of function units and hence to improve the throughput. Then we propose a comprehensive comparison of this new architecture with both some RSA architectures and other ECC implementations in ASIC VLSI technology
ECC hardware coprocessors for 8-bit systems and power consumption considerations
No full textIn the group of public key algorithms, Elliptic Curve Cryptosystems (or ECC) are widely considered as the best compromise in terms of speed, memory requirement and security level. Recent researches have stressed the possibility of implementing ECC in low-end systems such as the nodes of a Wireless Sensor Network (WSN). The main constraints for such an application are implementation cost and power consumption. The nodes of a WNS are battery-equipped systems, and battery lifetime is a premium factor. In this paper we propose two novel coprocessor architectures: a 12 Kgate processor able to perform one kP operation (i.e. the ECC primitive) over the finite field GF(2^163) in 17.05 ms, consuming 1.1 mJ of energy, and a 18.5 Kgate coprocessor performing the same operation in 14.68 ms but consuming only 0.66 mJ. Both represent an advancement with respect to known literature comparable solutions
Procedimento e sistema per la implementazione dell'algoritmo AES
No full textMethod and circuit for data encryption/decryptio
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