1,721,020 research outputs found
Issues in Embedded Single-Chip Multicore Architectures
No full textNowadays and future embedded and special purpose systems need a qualitative step forward in the research efforts better than continue in quantitatively improve the designs: it's time for scaling-out architectures, instead of scaling-up frequency. As transistor count is still increasing as expected by Moore's law, recent challenges like wire-delay, design complexity, and power requirements are becoming more and more important. These problems are preventing the evolution of chip architecture in the directions followed in the previous decades, when clock frequency as well could scale-up with Moore's law. Many researchers and companies have started to look at building multiprocessors on a single chip, following both past and novel design solutions: no doubt that we are all expecting several cores on a single chip in the near future
PHAST - A portable high-level modern C++ programming library for GPUs and multi-cores
No full textA decade after the beginning of the many-core era, multi-core CPU and GPU architectures are everywhere, from mobile devices up to high-performance workstations and servers. To this day, programmers willing to harness their power need to express their code via languages and frameworks that often lack of expressivity and high-level abstractions. These solutions, despite allowing users to reach unprecedented performance, can still be a hampering factor for productivity and portability. In this paper we propose PHAST, a modern C++, STL-like, single-source programming library and approach based on multi-dimensional dynamic containers and multilayered functors that can be targeted on NVIDIA GPUs and multi-core CPUs. Its main purpose is to let programmers write code once for different architectures at a high level of abstraction, to reach high-performance while allowing fine parameter tuning and not shielding code from low-level target-specific optimizations. To assess the value of our proposal, we consider benchmarks from different application domains, and we evaluate their PHAST implementations against CUDA, OpenCL, Kokkos, and SYCL ones from both performance and productivity points of view. We show that PHASTcan significantly reduce code complexity metrics while reaching very good performance
Simple Onchip Optical Interconnection for Improving Performance of Coherence Traffic in CMPs
No full textDesign options for optical ring interconnect in future client devices
No full textNanophotonic is a promising solution for on-chip interconnection due to its intrinsic low-latency and low-power features. Future tiled chip multiprocessors (CMPs) for rich client devices can receive energy benefits from this technology but we show that great care has to be put in the integration of the various involved facets to avoid queuing and serialization issues and obtain the rated potential advantages.
We evaluate different management strategies for accessing a simple, shared photonic path (ring), working in conjunctions with a standard electronic mesh or alone, in a tiled CMP. Our results highlight that a careful selection of the most latency-critical messages to be routed in photonics and the use of a conflict-free access scheme is crucial for obtaining performance/power advantages when the available bandwidth is limited.
We identify the design point where all the traffic can be routed on the photonic path and thus the electronic network can be suppressed. At this point, the ring achieves 20-25% speedup and 84% energy consumption improvement over the electronic baseline.
Then we investigate the same trade-offs when the number of rings is increased up to eight, allowing to raise performance benefits up to 40% or reaching up to 80% energy reduction. We finally explore the effects of deploying a given optical parallelism split between a higher number of waveguides for further improving energy savings
Transactions on High-Performance Embedded Architectures and Compilers - Special Issue on Memory Performances
No full textEmbedded Processors and Systems: Architectural Issues and Solutions for Emerging Applications
No full textEnsemble Methods for Peristaltic Pump Accuracy Enhancement
Full text linkThis study investigates how ensemble learning techniques can be employed for enhancing peristaltic pump accuracy in pharmaceutical manufacturing, and demonstrates significant accuracy improvements through the novel E-AR implementation, with gains of up to 53.93% at 0.3 ml volume compared to 47% achievable with single models. To establish the foundation for ensemble methods evaluation, we first conduct a comprehensive validation of traditional Adaptive Dosing Control System (ADCS) across an extended volume range (0.1-2.0 ml), demonstrating base performance improvements. In this investigation, we develop a novel offline performance indicator enabling rapid assessment of compensation strategies without extensive physical testing, showing strong correlation with actual measurements. These premises enable a thorough investigation of various ensemble configurations, revealing volume-dependent performance patterns where different models excel under specific conditions, suggesting that practical applications may benefit from volume-specific model selection. The comparison with a very accurate reference mechanical pump, demonstrates that our ADCS solutions achieve comparable or superior performance across most volumes while maintaining the cost-effectiveness. Statistical validation via a multi-dimensional framework confirms the significance of these improvements through multiple complementary tests: paired t-tests showing significant mean differences with p≤0.001, Mann-WhitneyUtests confirming distributional shifts, Levene tests demonstrating variance modifications with statistics up to 801.65, and mixed linear model analysis with F-statistics ranging from 0.004 to 1497.75 confirming global effects
Bluesign-2, il nuovo visualizzatore portatile per la Lingua Italiana dei Segni
No full textIl sistema Bluesign-2 e' stato realizzato su un computer palmare, sfruttando la possibilita' di ricevere messaggi SMS tramite la connessione alla rete telefonica cellulare. I messaggi vengono cosi' ricevuti o selezionati manualmente dall'utente e visualizzati in Lingua Italiana dei Segni utilizzando una figura animata tridimensionale (detta avatar). In questo articolo vengono presentati alcuni dei problemi risolti a livello di rendering dell'avatar e il funzionamento del dispositivo
Application of LSTM and GRU neural networks to improve peristaltic pump dosing accuracy
Full text linkPeristaltic pumps (PP), widely acknowledged for their benefits in pharmaceutical contexts, face challenges in achieving optimal dosing accuracy. This investigation contributes novel insights for the improvement of dosing precision, identifying how to apply AI models, specifically focusing on Long Short-Term Memory (LSTM) and Gated Recurrent Unit (GRU) neural networks over a realistic span of target volumes. To provide a more accurate representation of real-world performance, we consider a modified root mean square error metric (RMSEPP) that directly compares dispensed volumes to target volumes. Based on this the study delves into two main methodologies: an iterative retraining method, called Online Training, and Pre-trained approach. Online Training shows best results, especially for volumes below 1.0 ml, achieving 38.4% improvement in RMSEPP and 31.6% in standard deviation (STD). Pre-trained models are faster and exhibit promising outcomes especially for volumes above 1.0 ml, with a three-features approach delivering the best performance (13.8% and 4.6% improvements in RMSEPP and STD, respectively). Overall, the findings highlight the effectiveness of iterative learning techniques, particularly for smaller dosage amounts, which complements the good performance of non-AI approaches for larger ones
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