1,720,973 research outputs found
A software cache partitioning system for hash-based caches
Full text linkContention on the shared Last-Level Cache (LLC) can have a fundamental negative impact on the performance of applications executed on modern multicores. An interesting software approach to address LLC contention issues is based on page coloring, which is a software technique that attempts to achieve performance isolation by partitioning a shared cache through careful memory management. The key assumption of traditional page coloring is that the cache is physically addressed. However, recent multicore architectures (e.g., Intel Sandy Bridge and later) switched from a physical addressing scheme to a more complex scheme that involves a hash function. Traditional page coloring is ineffective on these recent architectures. In this article, we extend page coloring to work on these recent architectures by proposing a mechanism able to handle their hash-based LLC addressing scheme. Just as for traditional page coloring, the goal of this new mechanism is to deliver performance isolation by avoiding contention on the LLC, thus enabling predictable performance. We implement this mechanism in the Linux kernel, and evaluate it using several benchmarks from the SPEC CPU2006 and PARSEC 3.0 suites. Our results show that our solution is able to deliver performance isolation to concurrently running applications by enforcing partitioning of a Sandy Bridge LLC, which traditional page coloring techniques are not able to handle
HERA: Hardware evolution over reconfigurable architectures
No full textSince the birth of the Evolvable Hardware (EHW) research field (1993), many FPGA-based evolvable hardware techniques have been devised and proposed to the scientific community. Even if newer EHW systems introduce improvements and new features with respect to the older ones, in most cases they are still based on outdated FPGAs. Thus, they are often limited by the amount of available resources and by the capabilities of the devices used. This paper describes an EHW system based on a Xilinx Virtex-4 FPGA able to exploit features like the direct bitstream manipulation and the two-dimensional dynamic reconfiguration mechanism. Such system has been introduced in 2009 and has been refined in order to cope with real-world applications like the classification problem addressed in this paper
Characterizing Molecular Dynamics Simulation on Commodity Platforms
Full text linkMolecular Dynamics (MD) simulation is an essential tool driving innovation in key scientific domains such as physics, materials science, biochemistry, and drug discovery. Enabling larger, longer, and more accurate MD simulations can directly impact scientific discovery and innovation. While domain-specific architectures for MD exist, they are not widely accessible, and MD performance on commodity platforms (i.e., CPUs and GPUs) remains critical for supporting broad and agile scientific progress.
This paper aims at characterizing MD simulation on commodity platforms with a benchmark campaign on modern systems available in public cloud offerings. We focus on LAMMPS, one of the prevalent MD frameworks, and characterize several representative and diverse MD experiments. We find that the benchmarked CPU instance provides good scalability to many cores, while the reference LAMMPS GPU implementation struggles with scaling to multiple devices. Additionally, we evaluate the performance impact of application-specific parameters such as error threshold and arithmetic precision.
Our study indicates that key drivers for further improvement of LAMMPS performance on commodity systems are: 1) improving scalability and offload efficiency in multiaccelerator systems and 2) reducing work imbalance in the CPU parallelization
A Bird's Eye View of FPGA-based Evolvable Hardware
Full text linkThe Evolvable Hardware research area has achieved very important progresses in the last two decades. However, it is still quite far from being as revolutionary as depicted in the earlier visionary papers. To have a positive impact on the Embedded Design Automation field, Evolvable Hardware systems should start to deal with more complex problems instances efficiently. This paper describes some interesting results achieved so far in the Evolvable Hardware area and gives some hints on what should be done for increasing the efficiency of Evolvable Hardware systems
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