773,529 research outputs found
Scan architecture with mutually exclusive scan segment activation for shift and capture power reduction
No full textPower dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. While several approaches have been recently proposed for reducing power dissipation during the shift cycle (minimum transition don't care fill, special scan cells and scan chain partitioning), very little work has been carried out towards reducing the peak power during test response capture and the few existing approaches for reducing capture power rely on complex ATPG algorithms. This paper proposes a scan architecture with mutually exclusive scan segment activation which overcomes the shortcomings of previous approaches. The proposed architecture achieves both shift and capture power reduction with no impact on the performance of the design, and with minimal impact on area and testing time (typically 2-3%). An algorithmic procedure for assigning flip-flips to scan segments enables reuse of test patterns generated by standard ATPG tools. An implementation of the proposed method had been integrated into an automated design flow using commercial synthesis and simulation tools which was used on a wide range of benchmark designs. Reductions up to 57% in average power, and up to 44% and 34% in peak power dissipation during shift and capture cycles, respectively, were obtained when using two scan segments. Increasing the number of scan segments to six leads to reductions of 96% and 80% in average power and respectively maximum number of simultaneous transitions
Numerically efficient modeling of CNT transistors with ballistic and non-ballistic effects for circuit simulation
No full textThis paper presents an efficient carbon nanotube (CNT) transistor modeling technique which is based on cubic spline approximation of the non-equilibrium mobile charge density. The approximation facilitates the solution of the selfconsistent voltage equation in a carbon nanotube so that calculation of the CNT drain-source current is accelerated by at least two orders of magnitude. A salient feature of the proposed technique is its ability to incorporate both ballistic and nonballistic transport effects without a significant computational cost. The proposed models have been extensively validated against reported CNT ballistic and non-ballistic transport theories and experimental results
Dataset for "Optimising Resource Management for Embedded Machine Learning"
No full textDataset supports: Xun, L., Tran-Thanh, L., Al-Hashimi, B., & Merrett, G. (2019). Optimising resource management for embedded machine learning. In Design, Automation and Test in Europe Conference 2020 (DATE'20).</span
Dataset for "Incremental Training and Group Convolution Pruning for Runtime DNN Performance Scaling on Heterogeneous Embedded Platforms"
No full textDataset supports: Xun, L., Tran-Thanh, L., Al-Hashimi, B., & Merrett, G. (2019). Incremental Training and Group Convolution Pruning for Runtime DNN Performance Scaling on Heterogeneous Embedded Platforms. In ACM/IEEE Workshop on Machine Learning for CAD 2019 (MLCAD'19).</span
Diagnosis of Multiple-Voltage Design with Bridge Defect
No full textMultiple voltage is an effective dynamic power reduction design technique commonly used in low-power ICs. To the best of our knowledge, there is no reported work for diagnosing multiple-voltage enabled ICs, and the aim of this paper is to propose a method for diagnosing bridge defects in such ICs. By using synthesized ISCAS benchmarks, with realistic extracted bridges and a parametric fault model, this paper investigates the impact of varying supply voltage on the accuracy of diagnosis and demonstrates how the additional voltage settings can be leveraged to improve the diagnosis resolution through a novel multivoltage diagnosis algorithm. In addition, it also identifies the most useful voltage settings to reduce diagnosis cost by eliminating tests at certain voltage setting using the proposed multivoltage diagnosis approach, thereby achieving high diagnosis accuracy at reduced cost
Variation Resilient Adaptive Controller for Subthreshold Circuits
No full textSubthreshold logic is showing good promise as a viable ultra-low-power circuit design technique for power-limited applications. For this design technique to gain widespread adoption, one of the most pressing concerns is how to improve the robustness of subthreshold logic to process and temperature variations. We propose a variation resilient adaptive controller for subthreshold circuits with the following novel features: new sensor based on time-to-digital converter for capturing the variations accurately as digital signatures, and an all-digital DC-DC converter incorporating the sensor capable of generating an operating operating Vdd from 0V to 1.2V with a resolution of 18.75mV, suitable for subthreshold circuit operation. The benefits of the proposed controller is reflected with energy improvement of up to 55% compared to when no controller is employed. The detailed implementation and validation of the proposed controller is discussed
Dataset for Reliable Mapping and Partitioning of Performance-constrained OpenCL Applications on CPU-GPU MPSoCs
No full textDataset to support an invited paper for publication in 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia.
Weber Wachter, E., Merrett, G. V., Singh, A., & Al-Hashimi, B. (2017). Reliable mapping and partitioning of performance-constrained OpenCL Applications on CPU-GPU MPSoCs. Paper presented at 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia, Seoul, Korea, Republic of.</span
Analogue Filter IP Cores for Design Reuse
No full textThis paper addresses important considerations concerning the design of analogue filters, to ensure their suitability for use in a system on chip environment as intellectual property filter cores. We argue that switched-current is the most suitable circuit design technique and furthermore that the wave filter design methodology is favourable over an integrator approach. To speed up the design process some level of automation is clearly necessary and a system implemented in the SKILL language and within the Cadence Design Framework is particularly attractive given the access to powerful circuit analysis tools. A design flow is presented encompassing all of these attributes
A Fast and Accurate Process Variation-aware Modeling Technique for Resistive Bridge Defects
No full textRecent research has shown that tests generated without taking process variation into account may lead to loss of test quality. At present there is no efficient device-level modeling technique that models the effect of process variation on resistive bridge defects. This paper presents a fast and accurate technique to achieve this, including modeling the effect of voltage and temperature variation using BSIM4 transistor model. To speedup the computation time and without compromising simulation accuracy (achieved through BSIM4) two efficient voltage approximation algorithms are proposed for calculating logic threshold of driven gates and voltages on bridged lines of a fault-site to calculate bridge critical resistance. Experiments are conducted on a 65-nm gate library (for illustration purposes), and results show that on average the proposed modeling technique is more than 53 times faster and in the worst case, error in bridge critical resistance is 2.64% when compared with HSPICE
Research data for "A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder"
No full textDataset supporting:
Hailes, P., Xu, L., Maunder, R., Al-Hashimi, B., and Hanzo, L. (2017). A flexible FPGA-based quasi-cyclic LDPC decoder. IEEE Access. DOI: 10.1109/ACCESS.2017.2678103</span
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