1,721,491 research outputs found
Design of advanced LDPC decoders using traditional and new implementation technologies
No full textLow Density Parity Check (LDPC) codes, a class of linear block codes have gained
huge attention in digital communication domain. Binary LDPC codes were invented
by Gallager in 1963 and rediscovered by Mackay and Neil in 1995. Thanks to near
Shannon limit performance, low error floor, intrinsic parallelism and affordable com-
plexity, binary LDPC codes are considered in a number of standards e.g. WiMAX
(IEEE 802.16e), WiFi (IEEE 802.11n), WLAN and DVB-S2. Non binary LDPC
(NB-LDPC) codes, an extension of binary LDPC to higher order Galois fields, show
better performance when the code length is small or when a high-order modula-
tion is applied in the communication system. Apart from all the elegant features,
hardware design of LDPC decoders meeting area, power and speed constraints is
still a challenging task and requires considerable research effort. In this thesis we
focused our research towards efficient design of high performance LDPC decoders
using traditional CMOS VLSI and “beyond CMOS” technologies. This thesis has
contributions both in the domain of binary and non binary LDPC decoding. The
main contributions to this thesis are summarized in the following paragraphs.
The processing core of a binary LDPC decoder lies in the check node (CN)
part which executes actual decoding algorithm and contributes towards the overall
complexity, throughput and performance of the whole decoder. The state of the art
for LDPC decoders mainly features a partial parallel architecture which consists of
a number of CNs realized in hardware to achieve flexible, high throughput, iterative
decoding. However, in most of the published works on LDPC decoders, the CN
itself is implemented in a serial way which limits the achievable throughput to a
large extent. Realizing high throughput decoders (supporting data rates up to few
hundred Mbps) either asks for a massive number of CNs or a high clock frequency
which results in significant area and power overhead. Parallelism at check node level
is an essential step which can bring significant increase in throughput. However, a
straightforward parallel implementation suffers from large complexity of CN. So,
in the first part of the thesis we proposed a generic implementation of a parallel
check node based on a novel “Tree way” approach. In addition, we presented a
generalization of the “Tree-way” approach for check node degree dc up to 32, which
provides compile time flexibility to support a large number of LDPC codes for next
generation standards. The “Tree way” check node architecture is exploited to design
a fully parameterized LDPC decoder IP core forWiMAX andWiFi standards. With
the help of an efficient datapath reuse and simple control mechanism, the proposed
decoder based on “Tree way” check node achieves a high throughput with fairly
affordable complexity.
The second part of the thesis deals with the the VLSI hardware implementation
of a novel Belief Propagation (BP) algorithm named as Analog Digital Belief Prop-
agation (ADBP). The ADBP algorithm works on factor graphs over linear models and uses messages in the form of Gaussian like probability distributions by track-
ing their parameters. In particular, ADBP can deal with system variables that are
discrete and/or wrapped. A variant of ADBP can then be applied for the iterative
decoding of a particular class of NB-LDPC codes and yields decoders with complex-
ity independent of modulation alphabet size M, thus allowing to construct efficient
decoders for digital transmission systems with unbounded spectral efficiency. In this
work, we propose some simplifications to the updating rules for ADBP algorithm
that are suitable for hardware implementation. In addition, we analyze the effect of
finite precision on the decoding performance of the algorithm. A careful selection of
quantization scheme for input, output and intermediate variables allows us to con-
struct a complete ADBP decoding architecture that performs close to the double
precision implementation and shows a promising complexity for large values of M.
Because of the computation intensive nature of LDPC decoding algorithms, a
CMOS VLSI based implementation of LDPC decoders results in a considerable area
and power. In addition, the limitations on the switching frequency of CMOS transis-
tors puts an upper bound on the achievable throughput. Therefore, implementation
of LDPC decoders on advanced “beyond CMOS” technologies makes sense. Quan-
tum dot Cellular Automata (QCA) is an emerging nanotechnology that has gained
significant research interest in recent years. Extremely small feature sizes, ultra low
power consumption, and high clock frequency make QCA a potentially attractive
solution for implementing computing architectures at the nanoscale. In the third
part of the thesis we present a novel QCA architecture for binary LDPC check node
which executes Normalized Min Sum algorithm. We adapt the decoding architec-
ture to the specific characteristics of QCA technology, by exploiting majority voting
circuits and inherent delaying and pipelining behavior of wires. The proposed CN is
fully pipelined, partial parallel and reconfigurable to support up to degree dc = 20.
The circuit is described using a realistic layout aware VHDL model which allows
in addition to the circuit simulation, area and power estimation for the two im-
plementations of QCA technology i.e. magnetic and molecular. Simulation results
show that remarkable area saving and high throughput could be achieved for molec-
ular QCA implementation, while the magnetic QCA is attractive for achieving low
power. For both cases, the proposed design has an area fairly smaller and clock
speed comparable or much larger than its implementation on up to date CMOS
technology. Finally, we present a QCA implementation of Fast Fourier Transform
(FFT) Algorithm which has application in decoding of non binary LDPC codes.
A novel architecture for a partial parallel FFT processor is presented which not
only reduces the circuit complexity but also eliminates the need of feedback signals,
allowing to maximize the throughput. Again, the circuit performance results are
estimated with the help of a layout aware VHDL model for magnetic and molecular
QCA technologies
Physical activity classification meeting daily life conditions
Full text linkPhysical activity is one of the key factors in determining the personal health and well-being of human beings in daily life conditions. Healthy ageing and physical activity has a strong association and ageing has become one of the highly concentrated area of research community in the past decade due to the expected increase in the elderly population. A statistical survey published by European Union (EU) in 2012 shows that the elderly population (over 65 years) of Europe, is expected to increase from 87.5 million to 152.6 million (65.1 million increase) during the period from 2010 to 2016 [1]. Physical inactivity and more sedentary life style can lead towards many chronic and life threatening diseases in older adults such as diabetes, cancer, cardiovascular and other lethal diseases. These damages can be controlled by performing various activities and vigorous exercises in daily life, in addition to medications to promote a healthier lifestyle [2]
Flexible LDPC Decoder Architectures
Full text linkFlexible channel decoding is getting significance with the increase in number of wireless standards and modes within a standard. A flexible channel decoder is a solution providing interstandard and intrastandard support without change in hardware. However, the design of efficient implementation of flexible low-density parity-check (LDPC) code decoders satisfying area, speed, and power constraints is a challenging task and still requires considerable research effort. This paper provides an overview of state-of-the-art in the design of flexible LDPC decoders. The published solutions are evaluated at two levels of architectural design: the processing element (PE) and the interconnection structure. A qualitative and quantitative analysis
of different design choices is carried out, and comparison is provided in terms of achieved flexibility, throughput, decoding efficiency, and area (power) consumption
Nickel oxide photocathodes prepared using rapid discharge sintering for p-type dye-sensitized solar cells
Full text linkThis paper compares the photoelectrochemical performances of nickel oxide (NiO) thin films processed using two different sintering procedures: rapid discharge sintering (RDS) and conventional furnace sintering (CS). Prior to sintering, NiO nanoparticles were sprayed onto substrates to form loosely adherent nanoparticulate coatings. After RDS and furnace sintering the resultant NiO coatings were sensitized with erythrosine B dye and corresponding p-type dyesensitized solar cells were fabricated and characterized. NiO electrodes fabricated using the RDS technique exhibited a fourfold enhancement in electroactivity compared to CS electrodes. A possible explanation is the smaller sintered grain size and more open mesoporous structure achieved using the microwave plasma treatments
Quantum Dot Cellular Automata Check Node Implementation for LDPC Decoders
Full text linkThe quantum dot Cellular Automata (QCA) is an emerging nanotechnology that has gained significant research interest in recent years. Extremely small feature sizes, ultralow power consumption, and high clock frequency make QCA a potentially attractive solution for implementing computing architectures at the nanoscale. To be considered as a suitable CMOS substitute, the QCA technology must be able to implement complex real-time applications with affordable complexity. Low density parity check (LDPC) decoding is one of such applications. The core of LDPC decoding lies in the check node (CN) processing element which executes actual decoding algorithm and contributes toward overall performance and complexity of the LDPC decoder. This study presents a novel QCA architecture for partial parallel, layered LDPC check node. The CN executes Normalized Min Sum decoding algorithm and is flexible to support CN degree dc up to 20. The CN is constructed using a VHDL behavioral model of QCA elementary circuits which provides a hierarchical bottom up approach to evaluate the logical behavior, area, and power dissipation of the whole design. Performance evaluations are reported for the two main implementations of QCA i.e. molecular and magneti
Physical activity classification using body-worn inertial sensors in a multi-sensor setup
No full textPhysical inactivity significantly impacts personal health, reduces quality of life, and often leads to mobility disorders, diabetes, and cardiovascular disease. Monitoring daily life activities by means of wearable inertial sensors can provide valuable feedback necessary to improve the quality of daily life and prevent the development of mobility disorders caused by physical inactivity. In this study, a physical activity classification (PAC) algorithm was developed and tested using an inertial sensor-based dataset. The dataset was acquired from multiple inertial sensors, each mounted at a different body location, and consists of various Activities of Daily Living (ADL). Data from nineteen healthy young subjects were analyzed. Time- and frequency-domain features from raw 3D accelerometer and 3D gyroscope signals were computed by performing windowing of the time series data. The K-nearest neighbors (KNN) pattern recognition algorithm was used to classify thirteen different ADLs and was evaluated by a 10-fold cross-validation. The proposed PAC algorithm outperformed the existing algorithm validated using the same dataset, with an overall mean classification rate (sensitivity) of 97.38%. This paper discusses the limitations of this study and proposes ways to overcome said limitations in order to make the PAC algorithm more effective in real-life conditions
Physical activity classification meets daily life: Review on existing methodologies and open challenges
No full textRecent advances in the MEMS devices make it happen to wirelessly integrate miniature motion capturing devices with Smartphones and to use them in personal health care and physical activity monitoring in daily life. There is no ground truth, though, to measure the physical activity (PA) in daily life and because of this, there is no common validation procedure adapted by the researchers for benchmarking the performance of algorithms for PA classification. The major issue in the existing studies for PA classification is the utilization of structured protocol in a controlled setting or simulated daily environment, which limits their implementation in real life conditions where activities are unplanned and unstructured, both in occurrence and in duration. This study provides a critical review on the validation procedures used for PA classification, types of activities classified and limitations in the exiting studies to implement them in daily life settings. Only those studies are considered which classify PA based on wearable accelerometers as an objective measure. The pros and cons of existing methodologies are highlighted and future possibilities are addressed for the development of a robust PA classification system which is feasible under real life conditions
FFT implementation using QCA
No full textQuantum dot Cellular Automata (QCA) is an emerging nanotechnology paradigm that is currently being investigated as a possible CMOS substitute. It offers higher speed and lower area and power consumption than CMOS transistors. However, due to its intrinsic pipelined nature, QCA circuits suffer from serious throughput reductions due to feedback signals. As a consequence to fully exploit the true potential of this technology, circuits architecture must be designed with the aim to reduce or eliminate the presence of feedbacks. This work proposes as a relevant design case, the QCA implementation of Fast Fourier Transform (FFT) Algorithm. A novel architecture for partial parallel FFT processor is presented which not only reduces the circuit complexity but also eliminates the need of feedback signals, allowing to maximize the throughput. The proposed architecture is described using an accurate, layout aware VHDL model which is exploited in a hierarchical bottom up approach to evaluate the logical behavior, area and power dissipation of whole design. This innovative approach widely expands the field of application for QCA circuits
VLSI implementation of 16-point DCT for H.265/HEVC using walsh hadamard transform and lifting scheme
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