1,721,027 research outputs found
AC and phase sensing of nanowires for biosensing
No full textData supporting the paper "Crescentini, Marco, Rossi, Michele, Ashburn, Peter, Lombardini, Marta, Sangiorgi, Enrico, Morgan, Hywel and Tartagni, Marco (2016) AC and phase sensing of nanowires for biosensing. Biosensors, 6, (2), 1-14. (doi:10.3390/bios6020015)"</span
Investigation of boron diffusion in polysilicon and its application to the design of pnp polysilicon emitter bipolar transistors with shallow emitter junctions
No full textNumerically efficient modeling of CNT transistors with ballistic and non-ballistic effects for circuit simulation
Full text linkThis paper presents an efficient carbon nanotube (CNT) transistor modeling technique which is based on cubic spline approximation of the non-equilibrium mobile charge density. The approximation facilitates the solution of the selfconsistent voltage equation in a carbon nanotube so that calculation of the CNT drain-source current is accelerated by at least two orders of magnitude. A salient feature of the proposed technique is its ability to incorporate both ballistic and nonballistic transport effects without a significant computational cost. The proposed models have been extensively validated against reported CNT ballistic and non-ballistic transport theories and experimental results
Deep level dopant compensated Czochralski silicon substrates for MMICs
No full textThe requirement for high resistivity single crystal silicon substrates for microwave monolithic integrated circuit (MMIC) applications above 1 GHz has been underlined in the ITRS Roadmaps, 2007 and 2009. We show that the resistivity of standard Czochralski silicon (Cz-Si) wafers can be enhanced from nominally 50 ?cm to approximately 15 k?cm, measured at about 20 oC using compensation by deep level (DL) impurity states of gold (Au), which was implanted into Cz-Si. We proposed a fully encapsulated Au-doped handle wafer for a SOI wafer configuration to solve the problem of Au contamination of the active wafer. The details have been discussed in our previous publications and a patent. In the present paper, we show significant reduction of RF attenuation in 1-40 GHz range in the DL-doped Si wafers, measured using co-planar waveguide (CPW) test structures fabricated on the material. Notably, the DL-doped wafers have a bi-layer resistivity profile. Our full 3D electromagnetic simulations using Ansys/Ansoft HFSS show significant enhancement of the quality (Q) factor of spiral inductors made on the material
A CMOS-Compatible Rapid Vapor-Phase Doping Process for CMOS Scaling
No full textAn advanced CMOS process, which used rapid vapor-phase doping (RVD) for pMOSFETs and solid-phase diffusion (SPD) for nMOSFETs, has been developed. Using the RVD technique, a 40-nm-deep p-type extension with a sheet resistance as low as 400 Ω/sq has been realised. These RVD and SPD devices demonstrate excellent short-channel characteristics down to 0.1µm channel length and 40 percent higher drain current, compared with conventional devices with ion implanted source/drain (S/D) extensions, and high-speed circuit performance. We investigate the effect of the S/D extension structure on the device performance and find that a gate extension overlap of 25nm enables excellent dc and high-speed circuit performance in 0.1µm device
Low cost thin-film transistor nanoribbon sensors for detection of proteins using a miniature bead-based enzyme-linked immunosorbent assay (elisa)
No full textWe demonstrate a low cost thin-film transistor (TFT) nanoribbon sensor for measuring enzyme-substrate reactions. The sensor is used to measure the inflammatory biomarker C-reactive protein (CRP) in human serum using a miniature bead-based Enzyme-Linked Immunosorbent Assay (ELISA) with the sensor measuring pH. Rather than binding antibodies directly to the sensor surface, a magnetic bead-based ELISA was used. This keeps the functionalization steps and capture moieties away from the sensor surface, increasing the binding sites and improving speed and sensitivity. The ability to sense proteins in physiological buffer via enzyme activity overcomes the Debye length limitation associated with nano-biosensors
Drain current multiplication in thin pillar vertical MOSFETs due to depletion isolation and charge coupling
Full text linkDrain current multiplication in vertical MOSFETs due to body isolation by the drain depletion region and gate–gate charge coupling is investigated at pillar thicknesses in the range of 200–10 nm. For pillar thickness >120 nm depletion isolation does not occur and hence the body contact is found to be completely effective with no multiplication in drain current, whereas for pillar thicknesses <60 nm depletion isolation occurs for all drain biases and hence the body contact is ineffective. For intermediate pillar thicknesses of 60–120 nm, even though depletion isolation is apparent, the body contact is still effective in improving floating body effects and breakdown. At these intermediate pillar thicknesses, a kink is also observed in the output characteristics due to partial depletion isolation. The charging kink and the breakdown behavior are characterized as a function of pillar thickness, and a transition in the transistor behavior is seen at a pillar thickness of 60 nm. For pillar thickness greater than 60 nm, the voltage at which body charging occurs decreases (and the normalized breakdown current increases) with decreasing pillar thickness, whereas for pillar thickness less than 60 nm, the opposite trend is seen. The relative contributions to the drain current of depletion isolation and the inherent gate–gate charge coupling are quantified. For pillar thickness between 120 and 80 nm, the rise in the drain current is found to be mainly due to depletion isolation, whereas for pillar thicknesses <60 nm, the increase in the drain current is found to be governed by the inherent gate–gate charge coupling
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