1,720,997 research outputs found
System-in-package testing: problems and solutions
No full textSystem in package integrates multiple dies in a common package. Therefore, testing SiP technology is different from system on chip, which integrates multiple vendor parts. This article provides test strategies for known good die and known good substrate in the SiP. Case studies prove feasibility using the IEEE 1500 test structur
Effective Diagnostic Pattern Generation Strategy forTransition-Delay Faults in Full-Scan SOCs
No full textAbstract—Nanometric circuits and systems are increasingly susceptible to delay defects. This paper describes a strategy for the diagnosis of transition- delay faults in full-scan systems-on-a-chip (SOCs). The proposed methodology takes advantage of a suitably generated software-based self-test test set and of the scan-chains included in the final SOC design. Effectiveness and feasibility of the proposed approach were evaluated on a nanometric SOC test vehicle including an 8-bit microcontroller, some memory blocks and an arithmetic core, manufactured by STMicroelectronics. Results show that the proposed technique can achieve high diagnostic resolution while maintaining a reasonable application tim
A Mathematical Model to assess the influence of parallelism in a Semiconductor Back-End Test Floor
No full textThe testing of IC at package level may require complex flows. In such cases, when the shop floor is fed with lots of multiple product lines, the manufacturing execution can suffer of very low efficiency, throughput limitation and longer cycle time than expected. The present work proposes a Mixed Integer Linear Programming model to evaluate the operational efficiency of the shop floor under different loading conditions and various shop floor characteristics. In particular, our computational campaign uses realistic data to evaluate the impact of increased parallelism and the effect of different parallelism distribution on the operational efficiency
Evaluating the Impact of DfM Library Optimizations on Alpha-induced SEU Sensitivity in a Microprocessor Core
No full textThis paper presents and discusses the results of Alpha Single Event Upset (SEU) tests on an embedded 8051 microprocessor core implemented using three different standard cell libraries. Each library is based on a different Design for Manufacturability (DfM) optimization strategy; our goal is to understand how these strategies may affect the device sensitivity to alpha-induced Soft Errors. The three implementations are tested resorting to advanced Design for Testability (DfT) methodologies and radiation experiments results are compared. Electrical simulations of flip-flops are finally performed to propose physical motivations to the observed phenomena
Accelerated Analysis of Simulation Dumps through Parallelization on Multicore Architectures
No full textWith the explosion of off-the-shelf SoCs in terms of size and the advent of novel techniques related to failure modes, commercial ATPG and fault simulation engines can often be insufficient to measure the coverage of very specific metrics. In these cases, many researchers firstly store the simulation trace during the analysis phase. Then, they collect the desired statistics during a post-processing step. In this framework, the so-called Value Change Dump (VCD) is a very commonly used file format to record simulation traces. The target of this paper is twofold. From the one hand, we illustrate some Burn-In (BI) related metrics which cannot be evaluated by current commercial fault simulators and ATPG engines. These metrics are indeed based on a post-processing analysis of memory dumps in VCD format. From the other hand, we mitigate the evaluation time and the memory required to analyze huge VCD files by exploiting optimization techniques coming from modern programming features and smart parallelization. Adopting this strategy, we can analyze simulation dumps of more than 250 GBytes in less than one hour, showing improvements of two orders of magnitude over previous tools, with a consequent higher scalability and testability power
In-field Data Collection System through Logic BIST for large Automotive Systems-on-Chip
No full textEmbedded nano-electronic systems are becoming more prevalent in people's daily lives. As a result, chip and embedded system manufacturing has become increasingly complicated and huge in recent years. Considering safety-critical sectors, such as automotive, it is evident how managing system anomalies and defects becomes vital. Thus, it is necessary to develop and investigate innovative methodologies that can guarantee high reliability despite modern Systems-on-Chip's complexity in critical safety fields. Significant attempts were made to market incredibly reliable microelectronic components. In order to ensure the reliability of the devices, the Automotive field has also started focusing on collecting large amounts of data from car fleets. The data are collected in-field during the life cycle of the devices and create effective feedback for designers and manufacturers. This paper proposes a methodology to store and collect data from key-on and key-off tests performed by Logic BIST for an industrial case study produced by STMicroelectronics
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