1,737,760 research outputs found
Context-bounded model checking of LTL properties for ANSI-C software
No full textContext-bounded model checking has successfully been used to verify safety properties in multi-threaded systems automatically, even if they are implemented in low-level programming languages like ANSI-C. In this paper, we describe and experiment with an approach to extend context-bounded model checking to liveness properties expressed in linear-time temporal logic (LTL). Our approach converts the LTL formulae into Buechi-automata and then further into C monitor threads, which are interleaved with the execution of the program under test. This combined system is then checked using the ESBMC model checker. Since this approach explores a larger number of interleavings than normal context-bounded model checking, we use a state hashing technique which substantially reduces the number of redundant interleavings that are explored and so mitigates state space explosion. Our experimental results show that we can verify non-trivial properties in the firmware of a medical device
ANSI X9.82, Part 3 - Deterministic Random Bit Generators - DRAFT June 2004
No full textThis part of ANSI X9.82 defines techniques for the generation of random bits using deterministic methods. This part includes:
1. A model for a deterministic random bit generator,
2. Requirements for deterministic random bit generators,
3. Specifications for deterministic random bit generators that use hash functions, block ciphers and number theoretic problems,
4. Implementation issues, and
5. Assurance considerations.
The precise structure, design and development of a random bit generator is outside the scope of this standard
Zipper performance when mixing ADSL and VDSL in terms of reach and capacity
No full textIn this contribution we have examined how the maximum reach vary at different bit rates on a VDSL system, when different numbers of ADSL and VDSL systems share the same binder. In this context it is concluded that when using the Zipper duplex scheme, VDSL can coexist with ADSL in the same binder without a significant degradation in reach. Further, it is shown that the Zipper duplex scheme secure that ADSL is not disturbed by NEXT from VDSL The Zipper performance has also been compared with both a TDD proposal and a FDD proposal. The results from this comparison shows that Zipper outperforms FDD and TDD in terms of extended reach at all studied mixes of ADSL and VDSL sharing the same binder. For example with a moderate number (5) of ADSL disturbers, the Zipper reach is 150 meters longer than for TDD, and is 350 meters longer than for FDD when studying the medium range asymmetrical bit rate (26:3.2 Mbps).Godkänd; 1997; 20080221 (ysko)</p
Option for inband POTS and ISDN
No full textWe propose an option allowing VDSL to use the spectrum now reserved for narrowband services, such as POTS and ISDN. The main motives for the proposal are: 1) This option will provide lower network complexity and maintenance costs by avoiding duplicate line cards.2) We can increase the number of customers using VDSL for rates below 15 Mbps. This is because when VDSL can use the full spectrum, the reach can be significantly extended. For example, the reach increases by up to 1000 meters for a 2 Mbps symmetric service on TP1 in a central office based scenario.Godkänd; 1997; 20080221 (ysko)</p
SMT-based bounded model checking for embedded ANSI-C software
No full textPropositional bounded model checking has been applied successfully to verify embedded software but remains limited by increasing propositional formula sizes and the loss of high-level information during the translation preventing potential optimizations to reduce the state space to be explored. These limitations can be overcome by encoding high-level information in theories richer than propositional logic and using SMT solvers for the generated verification conditions. Here, we propose the application of different background theories and SMT solvers to the verification of embedded software written in ANSI-C in order to improve scalability and precision in a completely automatic way. We have modified and extended the encodings from previous SMT-based bounded model checkers to provide more accurate support for variables of finite bit width, bit-vector operations, arrays, structures, unions and pointers. We have integrated the CVC3, Boolector, and Z3 solvers with the CBMC front-end and evaluated them using both standard software model checking benchmarks and typical embedded software applications from telecommunications, control systems, and medical devices. The experiments show that our ESBMC model checker can analyze larger problems than existing tools and substantially reduce the verification time
Zipper : a duplex scheme for VDSL based on DMT
No full textA duplex scheme for DMT-based VDSL systems is presented here. It offers a solution to the problem with NEXT and near-echoes in broadband communications. The scheme has high duplex efficiency, low latency, and attractive transmit power features. However, hardware verification remains.Godkänd; 1997; 20080221 (ysko)</p
SMT-Based Bounded Model Checking for Embedded ANSI-C Software
No full textPropositional bounded model checking has been applied successfully to verify embedded software but is limited by the increasing propositional formula size and the loss of structure during the translation. These limitations can be reduced by encoding word-level information in theories richer than propositional logic and using SMT solvers for the generated verification conditions. Here, we investigate the application of different SMT solvers to the verification of embedded software written in ANSI-C. We have extended the encodings from previous SMT-based bounded model checkers to provide more accurate support for variables of finite bit width, bit-vector operations, arrays, structures, unions and pointers. We have integrated the CVC3, Boolector, and Z3 solvers with the CBMC front-end and evaluated them using both standard software model checking benchmarks and typical embedded software applications from telecommunications, control systems, and medical devices. The experiments show that our approach can analyze larger problems and substantially reduce the verification time
Australian National Sustainability Initiative (ANSI) Design
No full textThe Australian National Sustainability Initiative (ANSI) is a proposal for a living, working and\ud
learning centre that will address social, economic, environmental and ecological\ud
sustainability. ANSI was proposed some years ago by the Nature and Society Forum in\ud
Canberra to demonstrate truly sustainable design and a centre for sustainability education.\ud
Birkeland has developed the design concept, in which the built environment produces\ud
ecosystem services and supports endangered ecosystems. The proposal is being refined
Context-bounded model checking with ESBMC 1.17
Get PDFESBMC is a context-bounded symbolic model checker that allows the verification of single- and multi-threaded C code with shared variables and locks. ESBMC supports full ANSI-C, and can verify programs that make use of bit-level operations, arrays, pointers, structs, unions, memory allocation and floating-point arithmetic. It can reason about arithmetic under- and overflows, pointer safety, memory leaks, array bounds violations, atomicity and order violations, local and global deadlocks, data races, and user-specified assertions. However, as other bounded model checkers, ESBMC is in general incomplete
Pulse shaping with zipper : spectral compatibility and asynchrony
No full textWe have investigated what the effects of adding pulse shaping and windowing to a Zipper-VDSL system would be. By adding short, pulse-shaped wings to the DMT symbol and accepting the, say, 3 % efficiency loss, the spectral sidelobes of the DMT-symbol are reduced. This provides several attractive features including the following: · The pulse shaping in the transmitter reduces the out of band power of the DMT-signal. · The spectral compatibility with other systems such as ADSL and CAP-VDSL is enhanced. · It becomes feasible to use Zipper-VDSL in a time-asynchronous mode, where a VTU-R only synchronizes itself to its VTU-O, while the VTU-R / VTU-O pair may be asynchronous to all other transceiver pairs. · The pulse shaping gives some increase in the depth of spectral notches, for HAM-bands etc. The windowing is a part of a powerful RFI-ingress suppressing method as proposed by John Bingham, Amati.Godkänd; 1998; Bibliografisk uppgift: Standards project: T1E1.4: VDSL; 20080221 (ysko)</p
- …
