777 research outputs found
A Hybrid ADC for High Resolution: The Zoom ADC
No full textThis paper presents a dynamic zoom ADC for audio applications. It achieves 109-dB DR, 106-dB SNR, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating 1.12 mW and occupying only 0.16 mm2 in 0.16-μm CMOS. This translates to state-of-the-art energy and area efficiency. In this paper, the system- and circuit-level design of the ADC will be presented.Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Electronic Instrumentation(OLD)Applied Quantum ArchitecturesMicroelectronic
The Zoom ADC: An Energy Efficient ADC for High Resolution
No full textAnalog-to-digital converters (ADCs) are an indispensable part of the digital age we are living in, as they form the interface between physical reality and virtual reality. Higher ADC energy efficiency is the dominant focus of ADC design research due to the high impact of ADC energy consumption to total energy consumption of the systems they are employed in. The energy consumption of an ADC increases with its resolution within a given signal bandwidth, which makes the efficiency of high-resolution ADCs even more important. Although the average energy efficiency of ADCs improved orders of magnitude in the last two decades, the high energy consumption of high-resolution ADCs was still restrictive for a large range of applications. This thesis investigates how the zoom ADC architecture can achieve both highresolution and high energy efficiency.Electronic Instrumentatio
An Element-Matched Electromechanical ΔΣ ADC for Ultrasound Imaging
No full textThis paper presents a power- and area-efficient approach to digitizing the echo signals received by piezoelectric transducer elements, commonly used for ultrasound imaging. This technique utilizes such elements not only as sensors but also as the loop filter of an element-level δσ analog to digital converter (ADC). The receiver chain is thus greatly simplified, yielding savings in area and power. Every ADC becomes small enough to fit underneath a 150 μm × 150 μm transducer element, enabling simultaneous acquisition and digitization from all the elements in a 2-D array. This is especially valuable for miniature 3-D probes. Experimental results are reported for a prototype receiver chip with an array of 5×4 element-matched ADCs and a transducer array fabricated on top of the chip. Each ADC consumes 800 μW from a 1.8 V supply and achieves a SNR of 47 dB in a 75% bandwidth around a center frequency of 5 MHz.Accepted Author ManuscriptElectronic Instrumentatio
Versatile DAC-less successive approximation ADC architecture for medium speed data acquisition
No full textImplementation of the DAC is usually the bottleneck in designing a SAR ADC. Here an innovative DAC-less SAR (DLSAR) ADC architecture is presented which alleviates some drawbacks of the conventional SAR counterpart. The proposed DLSAR binary search algorithm is comprised of two arithmetic operations of division-by-two and subtraction to emulate the DAC function. The hardware of the DLSAR ADC is implemented using ordinary circuit building blocks of a SAR ADC but with less complexity and more robustness against PVT variations as DAC is removed. The developed DLSAR architecture is versatile so that the converter hardware could be readily reconfigured for different sampling rates and resolutions. Based on post-layout simulations in 0.18 μm CMOS process, the designed 8-bit DLSAR ADC consumes 150 μW of power at 2 MS/s including the asynchronous control logic circuit. The SFDR of the converter is up to 62 dB and the ENOB reaches 7.8 bits while it remains above 7.5 bits across most PVT corners without calibration. Also, by reconfiguring the DLSAR ADC to 9-bit resolution at 1 MS/s, the ENOB is generally around 8.2 bits achieving a scaled figure-of-merit (SFoM) better than 3.0 Ç/c-s.Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Bio-Electronic
A 6.3 μW 20 bit Incremental Zoom-ADC with 6 ppm INL and 1 μV Offset
No full textA 20-bit incremental ADC for battery-powered sensor applications is presented. It is based on an energy-efficient zoom ADC architecture, which employs a coarse 6-bit SAR conversion followed by a fine 15-bit ΔΣ conversion. To further improve its energy efficiency, the ADC employs integrators based on cascoded dynamic inverters for extra gain and PVT tolerance. Dynamic error correction techniques such as auto-zeroing, chopping and dynamic element matching are used to achieve both low offset and high linearity. Measurements show that the ADC achieves 20-bit resolution, 6 ppm INL and 1 μV offset in a conversion timeof 40 ms, while drawing only 3.5 μA current from a 1.8 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 182.7 dB. The 0.35 mm² chip was fabricated in a standard 0.16 μm CMOS process.Accepted Author ManuscriptElectronic Instrumentatio
The Zoom ADC: An Evolving Architecture
No full textZoom ADCs combine a coarse SAR ADC with a fine delta-sigma modulator (?SM) to efficiently obtain high energy efficiency and high dynamic range. This makes them well suited for use in various instrumentation and audio applications. However, zoom ADCs also have drawbacks. The use of over-ranging in their fine modulators may limit SNDR, large out-of-band interferers may cause slope overload, and the quantization noise of their coarse ADC may leak into the baseband. This chapter presents an overview of recent advances in zoom ADCs that tackle these challenges while maintaining high energy efficiency. Prototypes designed in standard 0.16 µm technology achieve SNDRs over 100 dB in bandwidths ranging from 1 to 24 kHz while consuming only hundreds of µWs.Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Electronic InstrumentationMicroelectronic
A 590 μw, 106.6 dB SNDR, 24 kHz BW Continuous-Time Zoom ADC with a Noise-Shaping 4-bit SAR ADC
No full textThis paper presents a continuous-Time zoom ADC for audio applications. It combines a 4-bit noise-shaping coarse SAR ADC and a fine delta-sigma modulator with a tail-resistor linearized OTA for improved linearity, energy efficiency, and handling of out-of-band interferers compared to previous designs. In 160 nm CMOS, the prototype chip occupies 0.36 mm2, achieves 107.2 dB SNR, 106.6 dB SNDR, and 107.3 dB dynamic range in a 24 kHz bandwidth while consuming 590 μW from a 1.8 V supply. This translates into a Schreier figure-of-merit (FoMs) of 183.4 dB and a FoMSNDR of 182.7 dB. Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Electronic InstrumentationMicroelectronic
A Continuous-Time Zoom ADC for Low-Power Audio Applications
No full textThis article presents a continuous-Time zoom analog to digital converter (ADC) for audio applications. It employs a high-speed asynchronous SAR ADC that dynamically updates the references of a continuous-Time delta-sigma modulator (CTDSM). Compared to previous switched-capacitor (SC) zoom ADCs, its input impedance is essentially resistive, which relaxes the power dissipation of its reference and input buffers. Fabricated in a 160-nm CMOS process, the ADC occupies 0.27 mm 2 and achieves 108.1-dB peak SNR, 106.4-dB peak signal to noise and distortion ratio (SNDR), and 108.5-dB dynamic range in a 20-kHz bandwidth while consuming 618 \mu \text{W}. This results in a Schreier figure of merit (FoM) of 183.6 dB. Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Electronic InstrumentationMicroelectronic
A Dynamic Zoom ADC for Instrumentation Applications
No full textAnalog to digital converters (ADCs) are critical blocks in most signal processing chains.Especially in low bandwidth applications, there exists a need to digitize signals with high resolution and accuracy, while at the same time, expending minimum energy.This thesis presents a dynamic zoom ADC for use in such applications. The zoom ADC employs a high-speed asynchronous SAR ADC which works in tandem with a fully differential ΔΣ ADC. Fabricated in a 0.16-μm CMOS process, the prototype occupies 0.26 mm2 and achieves 119.1 dB peak SNR, 118.1 dB peak SNDR and 120.3 dB dynamic range in a 1 kHz bandwidth, while consuming 280 μW; resulting in a Schreier FoM of 185.8 dB.Electrical Engineerin
A 10-b 330nW Third-Order Predictive SAR ADC Dedicated to Neural Recording Brain Implants
No full textThis paper reports on a predictive analog-todigital converter (ADC). The proposed ADC employs a linear predictive filter to prepare a prediction for the current sample based on the values of the previous digital codes. This leads to significant reduction in the mean bit cycle of the converter. It is shown in this work that this idea is significantly more effective for the digitization of biological signals (e.g., intra-cortical neural signals). Compared with other similar techniques available in the literature, the proposed predictive ADC is significantly more successful for small signal-to-noise ratios. The proposed algorithm results in 48% and 37% reduction in the converter’s mean bit cycle compared with the conventional and LSB-first structures, respectively. Designed and post-layout simulated in a 90-nm standard CMOS technology and operated at 200 kS/s with a supply voltage of 0.4 V, the 10-bit predictive ADC consumes 330 nW. The circuit occupies a core area of 0.025 mm2, achieves an ENOB of 9.42 bits, a figure-of-merit of 2.4 fJ/conv.-step, and an SFDR of 65.8 dB. The DNL and INL of the circuit are within 0.45 LSB and 0.56 LSB, respectively.Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Bio-Electronic
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